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- proceedingFebruary 2009
FPGA '09: Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
FPGA 2009 is the 17th annual meeting of the ACM International Symposium on Field-Programmable Gate Arrays. As we gather again in Monterey, CA, we welcome you to this premier conference for the presentation of the latest research and advances in all ...
- posterFebruary 2009
3D configuration caching for 2D FPGAs
- Alessandro Cevrero,
- Panagiotis Athanasopoulos,
- Hadi Parandeh-Afshar,
- Philip Brisk,
- Yusuf Lebebici,
- Paolo Ienne,
- Maurizio Skerlj
FPGA '09: Proceedings of the ACM/SIGDA international symposium on Field programmable gate arraysPage 286https://doi.org/10.1145/1508128.1508205This poster proposes the use of 3D integration technology to enable low-overhead reconfigurable computing. In our scheme, a 64 Megabyte DRAM array is stacked on top of an FPGA using face-to-face bonding, and caches up to 289 future configurations which ...
- posterFebruary 2009
Measuring and modeling variabilityusing low-cost FPGAs
FPGA '09: Proceedings of the ACM/SIGDA international symposium on Field programmable gate arraysPage 286https://doi.org/10.1145/1508128.1508204The focus of this paper is to measure and qualify high-level process variation models by measuring variability on FPGAs. Measurements are done with high spatial resolution and demonstrate how the high-resolution data matches two industry test cases. The ...
- posterFebruary 2009
A parallel/vectorized double-precision exponential core to accelerate computational science applications
FPGA '09: Proceedings of the ACM/SIGDA international symposium on Field programmable gate arraysPage 285https://doi.org/10.1145/1508128.1508198Many natural processes exhibit exponential decay and, consequently, computational scientists make extensive use of e-χx in computer simulation experiments. While it is common to implement transcendental functions (sine, cosine, exponentiation, etc.) in ...
- posterFebruary 2009
32-bit floating-point FPGA gaussian elimination
FPGA '09: Proceedings of the ACM/SIGDA international symposium on Field programmable gate arraysPages 283–284https://doi.org/10.1145/1508128.1508196The well-known Gaussian elimination (with partial pivoting) is a widely-used algorithm, one of traditional methods for solving dense linear systems of equations (LSEs). This paper presents a hardware-optimized variant of Gaussian elimination and its 32-...
- posterFebruary 2009
The input-aware dynamic adaptation of area and performance for reconfigurable accelerator
FPGA '09: Proceedings of the ACM/SIGDA international symposium on Field programmable gate arraysPage 281https://doi.org/10.1145/1508128.1508191Attaching reconfigurable loop accelerator to a processor is a promising way to improve the performance and efficiency of the system. It's usually to unroll a loop to increase the parallelism of a loop accelerator. While the higher degree a loop is ...
- posterFebruary 2009
Performance and power of cache-based reconfigurable computing
- Andrew Putnam,
- Susan Eggers,
- Dave Bennett,
- Eric Dellinger,
- Jeff Mason,
- Henry Styles,
- Prasanna Sundararajan,
- Ralph Wittig
FPGA '09: Proceedings of the ACM/SIGDA international symposium on Field programmable gate arraysPage 281https://doi.org/10.1145/1508128.1508189CHiMPS is a C-based compiler for high-performance computing (HPC) on heterogeneous CPU-FPGA computing platforms. CHiMPS efficiently supports random accesses to main memory through the many-cache memory model, enabling a broader range of applications to ...
- short-paperFebruary 2009
Bus mastering PCI express in an FPGA
FPGA '09: Proceedings of the ACM/SIGDA international symposium on Field programmable gate arraysPages 273–276https://doi.org/10.1145/1508128.1508176This paper describes a bus mastering implementation of the PCI Express protocol using a Xilinx FPGA. While the theoretical peak performance of PCI Express is quite high, attaining that performance is a complex endeavor on top of an already complex ...
- short-paperFebruary 2009
PERG-Rx: a hardware pattern-matching engine supporting limited regular expressions
FPGA '09: Proceedings of the ACM/SIGDA international symposium on Field programmable gate arraysPages 257–260https://doi.org/10.1145/1508128.1508171PERG is a pattern matching engine designed for locating pre-defined byte string patterns (rules) from the ClamAV virus signature database in a data stream. This paper presents PERG-Rx, an extension of PERG that adds limited regular expression support ...
- short-paperFebruary 2009
A communication architecture for complex runtime reconfigurable systems and its implementation on spartan-3 FPGAs
FPGA '09: Proceedings of the ACM/SIGDA international symposium on Field programmable gate arraysPages 253–256https://doi.org/10.1145/1508128.1508170In this paper, we present and analyze a sophisticated communication architecture that allows to integrate many different modules into a system by FPGA reconfiguration at runtime. Furthermore, we examine how this architecture can be implemented on low-...
- short-paperFebruary 2009
A high performance fpga-based implementation of position specific iterated blast
FPGA '09: Proceedings of the ACM/SIGDA international symposium on Field programmable gate arraysPages 249–252https://doi.org/10.1145/1508128.1508169We present in this paper the first reported FPGA implementation of the Position Specific Iterated BLAST (PSI-BLAST) algorithm. The latter is a heuristic biological sequence alignment algorithm that is widely used in the bioinformatics and computational ...
- short-paperFebruary 2009
Cholesky decomposition using fused datapath synthesis
FPGA '09: Proceedings of the ACM/SIGDA international symposium on Field programmable gate arraysPages 241–244https://doi.org/10.1145/1508128.1508166In this paper we present an implementation of a Cholesky decomposition core, with IEEE754 single precision arithmetic. The datapaths are generated using fused datapath synthesis, created with an experimental floating point compiler tool, capable of ...
- research-articleFebruary 2009
Flexible multi-mode embedded floating-point unit for field programmable gate arrays
FPGA '09: Proceedings of the ACM/SIGDA international symposium on Field programmable gate arraysPages 171–180https://doi.org/10.1145/1508128.1508155Performance of Field Programmable Gate Arrays (FPGAs) used for floating-point applications is poor due to the complexity of floating-point arithmetic. Implementing floating-point units on FPGAs consume a large amount of resources. This makes FPGAs less ...
- research-articleFebruary 2009
Architectural enhancements in Stratix-III™ and Stratix-IV™
FPGA '09: Proceedings of the ACM/SIGDA international symposium on Field programmable gate arraysPages 33–42https://doi.org/10.1145/1508128.1508135This paper describes architectural enhancements in the Stratix-III" and Stratix-IV" FPGA architectures. These architectures feature programmable power management, which allows the power and performance of logic and routing to be varied to minimize total ...
- tutorialFebruary 2009
Emerging application domains: research challenges and opportunities for FPGAs
FPGA '09: Proceedings of the ACM/SIGDA international symposium on Field programmable gate arraysPages 1–2https://doi.org/10.1145/1508128.1508129Communications infrastructure, data processing and industrial electronics are the cornerstone application areas for programmable logic today. But what are the application domains of tomorrow? What nascent application areas could explode the growth of ...