Continual learning (CL) is a key advancement in artificial intelligence, enabling systems to learn and adapt over time. We introduce the concept and features of how to approach CL in silicon, with early examples from the literature.

Three-dimensional heterogeneous integration offers compelling opportunities to enhance the security and trust in the current semiconductor chain while new attack surfaces may emerge.

This article highlights the state of the art and critical challenges with lithography and patterning in metrology in enabling yield in next-generation high-volume manufacturing of semiconductors. Each of these technology sectors are presented with respect ...

The Internet of Things provides exciting new capabilities as well as an alternative model for semiconductors--the deployment of vast numbers of small chips-but its success will require solving new VLSI design challenges.

Researchers have been studying threshold logic gates for more than 70 years, but industry has largely ignored this design approach because of the dominance of Boolean logic and CMOS fabrication. But emerging technologies, such as memristors, are making ...

Topics include an energy-efficient supercomputer, a new standard for high-bandwidth vertical interconnects between different layers of the same 3D chip, the hijacking of several domain names belonging to the agency responsible for coordinating the ...

Warp processing dynamically and transparently transforms an executing microprocessor's binary kernels into customized field-programmable gate array (FPGA) circuits, commonly resulting in 2X to 100X speedup over executing on microprocessors. A new ...

Hardwired ASICs—50X more efficient than programmable processors—sacrifice programmability to meet the efficiency requirements of demanding embedded systems. Programmable processors use energy mostly to supply instructions and data to the arithmetic ...

Emerging research device technologies might first appear in special applications that can extend conventional general-purpose processors along one of several axes. These applications could optimize the performance of future workloads such as recognition,...

ARM and its partners are trying to build more powerful handheld computing devices, while Intel is trying to make a handheld PC based on the company's x86 architecture.

Several high-performance computers now use field-programmable gate arrays as reconfigurable coprocessors. The authors describe the two major contemporary HPRC architectures and explore the pros and cons of each using representative applications from ...

Chip and PIN technology was introduced as a means of decreasing payment-card fraud. However, according to results of a two-phase experiment, the technology makes it easier for thieves to obtain PINs and more difficult for customers to defend against ...

Expanding the software concept to spatial models like circuits will facilitate programming next-generation embedded systems.

A vector case study shows how new functionality can be added to extend the 80x86 and PowerPC architectures to support a full vector architecture, primarily by enhancing their multimedia extensions to provide a better model for compilers and an easier-to-...

High-performance reconfigurable computers have the potential to exploit coarse-grained functional parallelism as well as fine-grained instruction-level parallelism through direct hardware execution on FPGAs.

Numerous application areas, including bioinformatics and computational biology, demand increasing amounts of processing capability. In many cases, the computation cores and data types are suited to field-programmable gate arrays. The challenge is ...

A field-programmable gate array implementation of a molecular dynamics simulation method reduces the microprocessor time-to-solution by a factor of three while using only high-level languages. The application speedup on FPGA devices increases with the ...

Unlocking the potential of field-programmable gate arrays requires compilers that translate algorithmic high-level language code into hardware circuits. The Trident open source compiler translates C code to a hardware circuit description, providing ...

To avoid the loss of sensitive or other important information stored on computers, companies are increasingly adopting hardware-based encryption, which offers faster performance and causes less strain on a host system's processing resources.

Using a high-level-language to hardware-description-language compiler and some novel architectures and algorithms to map twowell-known double-precision floating-point sparse matrix iterative-linear-equation solvers--the Jacobi and conjugate gradient ...