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- research-articleMarch 2024
Response surface methodology based synchronous multi-performance optimization of CMOS low-dropout regulator
AbstractAn easy-to-use efficient auto-design approach to achieve a synchronous optimization and solution for multiple performance objectives of a CMOS low-dropout regulator (LDO) circuit is proposed. As a core algorithm, response surface methodology (RSM)...
- research-articleMarch 2024
Fin core dimensionality and corner effect in dual core gate-all-around FinFET
AbstractThis article proposes investigation of low power performance of a fin field-effect transistor (FinFET) with surrounding gates through a calibrated technology computer-aided design (TCAD) framework. The proposed silicon body FinFET has a dual core ...
- research-articleFebruary 2024
An efficient adaptive routing algorithm for the Co-optimization of fault tolerance and congestion awareness based on 3D NoC
AbstractIn this paper, we propose an adaptive, fault-tolerant, and congestion-aware (AFTC) routing algorithm. It improves the overall network performance of three-dimensional Network-on-Chip (3D NoC) in terms of deadlock-free, adaptability, fault ...
- research-articleNovember 2023
A high-performance fully adaptive routing based on software defined network-on-chip
AbstractAdaptive routing techniques have been proven to be effective solutions for handling network congestion and enhancing the performance of Network-on-Chip (NoC). Traditional adaptive routing algorithms may degrade flexibility and lead to the issue ...
- research-articleNovember 2023
Frequency response and transient analysis of through glass packaging vias using matrix-rational approximation (MRA) technique for three-dimensional ICs
AbstractIn this paper, a computationally efficient matrix rational approximation (MRA) technique is developed to analyze the electrical behaviour of through packaging vias in glass interposer (TGVs). Using MRA technique, the electrical behaviour of TGVs ...
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- research-articleMarch 2023
Fast and accurate proximity effect correction algorithm based on pattern edge shape adjustment for electron beam lithography
AbstractThis paper proposes a fast and accurate shape-based proximity effect correction (PEC) algorithm based on pattern edge shape adjustment (PESA) for electron beam lithography (EBL). By performing PEC calculations with three layout sizes (1 μm, 2 μm, ...
- research-articleMarch 2023
Numerical assessment of dielectrically-modulated short- double-gate PNPN TFET-based label-free biosensor
AbstractA comprehensive investigation of dielectrically modulated Ge-source short double-gate PNPN tunnel FET (SG-PNPN TFET) based label-free biosensor is presented. Short gates and counter-doped pockets in the SG-PNPN TFET architecture improve band-to-...
- research-articleNovember 2022
A compact and cost effective quasi-in-situ method to characterize broadband RF shielding effectiveness of materials for advanced microelectronic packaging
AbstractAt present, one of the major measures to suppress electromagnetic (EM) radiation inside advanced integrated microelectronic packages is the proper placement of electromagnetic shielding. Existing shielding effectiveness (SE) ...
- research-articleNovember 2022
Compact high-performance dual-frequency power divider based on TSV
AbstractIn this paper, a dual-frequency compact power divider based on silicon via (TSV) is proposed. The matrix analysis method is used to convert the microstrip structure into Π-type structure, which improves the integration of the circuit. ...
- research-articleOctober 2022
A stable voltage island-driven floorplanning with fixed-outline constraint for low power SoC
AbstractThe multiple supply voltage technique is an effective method to address the challenge of chip power consumption. Voltage islands reduce the complexity of the power supply network during floorplanning of low-power systems-on-chip. In ...
- research-articleSeptember 2022
A reconfigurable millimeter-wave wideband low-noise amplifier in 55-nm CMOS
AbstractThis paper presents a dual-wideband millimeter-wave (mm-wave) low-noise amplifier (LNA) that can be reconfigured covering dual bandwidths of 22.8–28.9 GHz and 23.2–29.5 GHz by RF-switched passive inductors for 5G applications. The ...
- research-articleSeptember 2022
High-performance polymer top-contact thin-film transistor with orthogonal photolithographic process
AbstractBased on fluorinated photoresist, an orthogonal lift-off process was introduced to directly fabricate patterning metallic source and drain contacts on polymeric thin films to obtain the top-contact structure device. Top-contact ...
- research-articleAugust 2022
Proposal and analysis of carbon nanotube based differential multibit through glass vias
AbstractThe paper proposes glass as a potential material to advanced interposers for high-density three-dimensional (3-D) integration. On the basis of multi-bit through glass via (TGV) which comprises of TGVs filled with multi-walled carbon ...
- research-articleAugust 2022
ASAP5: A predictive PDK for the 5 nm node
AbstractWe present a predictive process design kit (PDK) for the 5 nm technology node, the ASAP5 PDK. ASAP5 is not related to a particular foundry and the assumptions are derived from literature. It incorporates several innovations that the ...
- research-articleJuly 2022
Analysis and characterization of layout dependent effect for advance FinFET circuit design
AbstractLayout dependent effects (LDEs) will cause electrical variation of FinFET circuits and even lead to manufacture failure in advanced technology stage. In this paper, we study the stress-correlated LDEs in FinFET device and found that ...
Highlights- Test structures of four stress-related layout dependent effects (LDEs) were designed based on their mechanisms.
- research-articleJanuary 2022
Fabrication and high-frequency characterization of low-cost fan-in/out WLP technology with RDL for 2.5D/3D heterogeneous integration
AbstractRedistribution layer (RDL) and through silicon via (TSV) are the two main important packaging methods of the heterogeneous integration, here we report on the interconnection characteristics in Fan-in/out wafer level packaging (WLP) ...
- research-articleJanuary 2022
Optimization of heterogeneous interconnection transmission based on impedance matching for 3-D IC high-frequency application
AbstractThrough-silicon via (TSV) is becoming an optimizing interconnection to realize high density, three-dimensional (3-D) integration system. However, its high-frequency application is limited due to the serious parasitic effect, impedance ...
- research-articleOctober 2021
Stochastic estimation of total radiated power from PCB signal/PDN layout using EMI radiation resistance
AbstractIn this article, a stochastic model is proposed for estimation of electromagnetic radiated emission from printed circuit board (PCB) layout. Considering the arbitrary nature of the PCB layout by radiation resistance, the radiated power ...
- research-articleOctober 2021
Vertical traversal approach towards TSVs optimisation over multilayer network on chip (NoC)
AbstractIn symmetric 3-D chip stacking, TSVs plays an important role and provides denser and fine pitches. The number of vertical links in 3-D mesh NoC topology is equal to 2 ( N − ( N 2 3 ) ), where N is the number of network nodes. The TSVs ...
Highlights- Study has discussed the analytical model of seven port routers to express the average number of packets at equilibrium conditions over the physical and ...
- research-articleOctober 2021
Enhanced pin-access prediction and design optimization with machine learning integration
AbstractIn daily increasing integrated circuit complexity, standard cell pin accessibility is becoming more significant part of design process. As pin density is increasing, fast and efficient algorithms for pin-access prediction and ...