Silicon physical unclonable functions (PUF) utilize fabrication variation to extract information that will be unique for each chip. However, fabrication variation has a very strong spatial correlation and thus the PUF information will not be ...

With technology scaling, integrated circuits (ICs) suffer from increasing process, voltage, and temperature (PVT) variations and adverse aging effects. In most cases, these reliability threats manifest themselves as timing errors on critical speed-paths ...

Statistical static timing analysis (SSTA) involves computation of maximum (max) and minimum (min) of Gaussian random variables. Typically, the max or min of a set of Gaussians is performed iteratively in a pair-wise fashion, wherein the result of each ...

TSV-to-TSV coupling is a new parasitic element in 3D ICs and can become a significant source of signal integrity problem. Existing studies on its extraction, however, becomes highly inaccurate when handling more than two TSVs on full-chip scale. In this ...

In this paper, we present a first general purpose GPU thermal management design that consists of both hardware architecture and OS scheduler changes. Our techniques schedule thread blocks from multiple computational kernels in spatial, temporal, and ...

In this paper, we propose an efficient iterative optimization based approach for architectural synthesis of dark silicon heterogeneous chip multi-processors (CMPs). The goal is to determine the optimal number of cores of each type to provision the CMP ...

Task-accurate performance estimation methods are widely applied in early design phases to explore different architecture options. These methods rely on accurate annotations generated by software profiling or real measurements to guarantee accurate ...

Technology scaling is a common trend in current embedded systems. It has promoted the use of multi-core, multi-processor, and distributed platforms. Such systems usually require run-time migration of distributed applications between the different nodes ...

The write endurance of NAND flash memory adversely impacts the lifetime of flash devices. A flash cell is likely to wear out after undergoing excessive program/erase (P/E) flips. Wear leveling is hence employed to spread erase operations as evenly as ...

MLC Flash memory is getting more popular in computer systems ranging from sensor networks and embedded systems to large-scale server systems. However, MLC flash has many reliability concerns, including the potential for corruption due to supply voltage ...

Heterogeneous systems-on-chip pose a challenge for power delivery given the variety of needs for different components. In this paper, we describe recent work that leverages power switches and conventional EDA toolflows to implement a set of power ...

Due to a significant mismatch between the objectives of wirelength and routing congestion, the routability issue is becoming more and more important in VLSI design. In this paper, we present a high quality placer Ripple 2.0 to solve the routability-...

IC performance, power dissipation, size, and signal integrity are now dominated by interconnects. However, with ever-shrinking standard cells, blind minimization of interconnect during placement causes routing failures. Hence, we develop Coordinated ...

Safety-critical systems require guarantees on their worst-case execution times. This requires modelling of speculative hardware features such as caches that are tailored to improve the average-case performance, while ignoring the worst case, which ...

The great availability of massively parallel computing platforms gives rise a question to the EDA industry--how can this be really helping the productivity of circuit designs. Scalability of traditional parallel methods have shown to be limited as the ...

Adaptive time-stepping is crucially important for the efficiency of a circuit simulator. Existing time-stepping methods rely on information at prior time point(s) to select step sizes, which can be problematic when the circuit is undergoing a fast ...

Emerging power-supply-on-chip applications such as on-chip DC-DC conversion, energy harvesting, and LED drivers use switching regulator ICs integrated with digital controllers. Although the resulting mixed-signal systems call for efficient system-level ...

The main goal of this paper is to expose the EDA community to the emerging class of circuits operating with single quanta of energy (e.g. photons or electrical carriers). We describe recent developments in the field of single-photon detection and single-...

This paper presents an innovative architecture for radiation-hardened FPGA (Field Programmable Gate Array). This architecture is based on the use of MTJs (Magnetic Tunnel Junctions), magnetic nanostructures used as basic elements of MRAM (Magnetic ...

In addition to scaling semiconductor devices down to their physical limit, novel devices show enhanced functionality compared to conventional CMOS. At advanced technology nodes, many devices exhibit ambipolar behavior, i.e., they show n- and p-type ...