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- research-articleJanuary 2019
Translating Timing into an Architecture: The Synergy of COTSon and HLS (Domain Expertise—Designing a Computer Architecture via HLS)
International Journal of Reconfigurable Computing (IJRC), Volume 2019https://doi.org/10.1155/2019/2624938Translating a system requirement into a low-level representation (e.g., register transfer level or RTL) is the typical goal of the design of FPGA-based systems. However, the Design Space Exploration (DSE) needed to identify the final architecture ...
- articleJanuary 2013
A heuristic scheduler for port-constrained floating-point pipelines
International Journal of Reconfigurable Computing (IJRC), Volume 2013Article No.: 1, Page 1https://doi.org/10.1155/2013/849545We describe a heuristic scheduling approach for optimizing floating-point pipelines subject to input port constraints. The objective of our technique is to maximize functional unit reuse while minimizing the following performance metrics in the ...
- articleJanuary 2013
Development of a soc for digital television set-top box: architecture and system integration issues
International Journal of Reconfigurable Computing (IJRC), Volume 2013Article No.: 1, Page 1https://doi.org/10.1155/2013/783501This work presents the integration of several IPs to generate a system-on-chip (SoC) for digital television set-top box compliant to the SBTVD standard. Embedded consumer electronics for multimedia applications like video processing systems require ...
- articleJanuary 2012
Algorithm and hardware design of a fast intra frame mode decision module for H.264/AVC encoders
International Journal of Reconfigurable Computing (IJRC), Volume 2012Article No.: 8, Page 8In the rate-distortion optimization (RDO), the process of choosing the best prediction mode is performed through exhaustive executions of the whole encoding process, increasing significantly the encoder computational complexity. Considering H.264/AVC ...
- articleJanuary 2012
A memory hierarchy model based on data reuse for full-search motion estimation on high-definition digital videos
International Journal of Reconfigurable Computing (IJRC), Volume 2012Article No.: 2, Page 2https://doi.org/10.1155/2012/473725The motion estimation is the most complex module in a video encoder requiring a high processing throughput and high memory bandwidth, mainly when the focus is high-definition videos. The throughput problem can be solved increasing the parallelism in the ...
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- articleJanuary 2012
Modeling and implementation of a power estimation methodology for systemC
International Journal of Reconfigurable Computing (IJRC), Volume 2012Article No.: 5, Page 5https://doi.org/10.1155/2012/439727This work describes a methodology to model power consumption of logic modules. A detailed mathematical model is presented and incorporated in a tool for translation of models written in VHDL to SystemC. The functionality for implicit power monitoring ...
- articleJanuary 2012
Adaptive multiclient network-on-chip memory core: hardware architecture, software abstraction layer, and application exploration
International Journal of Reconfigurable Computing (IJRC), Volume 2012Article No.: 5, Page 5https://doi.org/10.1155/2012/298561This paper presents the hardware architecture and the software abstraction layer of an adaptive multiclient Network-on-Chip (NoC) memory core. The memory core supports the flexibility of a heterogeneous FPGA-based runtime adaptive multiprocessor system ...
- articleJanuary 2012
Configurable transmitter and systolic channel estimator architectures for data-dependent superimposed training communications systems
International Journal of Reconfigurable Computing (IJRC), Volume 2012Article No.: 4, Page 4https://doi.org/10.1155/2012/236372In this paper, a configurable superimposed training (ST)/data-dependent ST (DDST) transmitter and architecture based on array processors (APs) for DDST channel estimation are presented. Both architectures, designed under full-hardware paradigm, were ...
- articleJanuary 2012
Efficient execution of networked MPSoC models by exploiting multiple platform levels
International Journal of Reconfigurable Computing (IJRC), Volume 2012Article No.: 6, Page 6Novel embedded applications are characterized by increasing requirements on processing performance as well as the demand for communication between several or many devices. Networked Multiprocessor System-on-Chips (MPSoCs) are a possible solution to cope ...
- articleJanuary 2012
A convolve-and-merge approach for exact computations on high-performance reconfigurable computers
International Journal of Reconfigurable Computing (IJRC), Volume 2012Article No.: 8, Page 8https://doi.org/10.1155/2012/925864This work presents an approach for accelerating arbitrary-precision arithmetic on high-performance reconfigurable computers (HPRCs). Although faster and smaller, fixed-precision arithmetic has inherent rounding and overflow problems that can cause ...
- articleJanuary 2012
NCOR: an FPGA-friendly nonblocking data cache for soft processors with runahead execution
International Journal of Reconfigurable Computing (IJRC), Volume 2012Article No.: 6, Page 6https://doi.org/10.1155/2012/915178Soft processors often use data caches to reduce the gap between processor and main memory speeds. To achieve high efficiency, simple, blocking caches are used. Such caches are not appropriate for processor designs such as Runahead and out-of-order ...
- articleJanuary 2012
Open systemc simulator with support for power gating design
International Journal of Reconfigurable Computing (IJRC), Volume 2012Article No.: 9, Page 9https://doi.org/10.1155/2012/793190Power gating is one of the most efficient power consumption reduction techniques. However, when applied in several different parts of a complex design, functional verification becomes a challenge. Lately, the verification process of this technique has ...
- articleJanuary 2012
An optimization-based reconfigurable design for a 6-bit 11-MHz parallel pipeline ADC with double-sampling S&H
International Journal of Reconfigurable Computing (IJRC), Volume 2012Article No.: 7, Page 7https://doi.org/10.1155/2012/786205This paper presents a 6 bit, 11MS/s time-interleaved pipeline A/D converter design. The specification process, from block level to elementary circuits, is gradually covered to draw a design methodology. Both power consumption and mismatch between the ...
- articleJanuary 2012
High performance biological pairwise sequence alignment: FPGA versus GPU versus cell BE versus GPP
International Journal of Reconfigurable Computing (IJRC), Volume 2012Article No.: 7, Page 7https://doi.org/10.1155/2012/752910This paper explores the pros and cons of reconfigurable computing in the form of FPGAs for high performance efficient computing. In particular, the paper presents the results of a comparative study between three different acceleration technologies, ...
- articleJanuary 2012
Optimizing investment strategies with the reconfigurable hardware platform RIVYERA
International Journal of Reconfigurable Computing (IJRC), Volume 2012Article No.: 6, Page 6https://doi.org/10.1155/2012/646984The hardware structure of a processing element used for optimization of an investment strategy for financial markets is presented. It is shown how this processing element can be multiply implemented on the massively parallel FPGA-machine RIVYERA. This ...
- articleJanuary 2012
Placing multimode streaming applications on dynamically partially reconfigurable architectures
International Journal of Reconfigurable Computing (IJRC), Volume 2012Article No.: 9, Page 9https://doi.org/10.1155/2012/608312By means of partial reconfiguration, parts of the hardware can be dynamically exchanged at runtime. This allows that streaming application running in differentmodes of the systems can share resources. In this paper, we discuss the architectural issues ...
- articleJanuary 2012
QoSS hierarchical NoC-based architecture for MPSoC dynamic protection
International Journal of Reconfigurable Computing (IJRC), Volume 2012Article No.: 3, Page 3https://doi.org/10.1155/2012/578363As electronic systems are pervading our lives, MPSoC (multiprocessor system-on-chip) security is becoming an important requirement. MPSoCs are able to support multiple applications on the same chip. The challenge is to provide MPSoC security that makes ...
- articleJanuary 2012
Exploring many-core design templates for FPGAs and ASICs
- Ilia Lebedev,
- Christopher Fletcher,
- Shaoyi Cheng,
- James Martin,
- Austin Doupnik,
- Daniel Burke,
- Mingjie Lin,
- John Wawrzynek
International Journal of Reconfigurable Computing (IJRC), Volume 2012Article No.: 8, Page 8https://doi.org/10.1155/2012/439141We present a highly productive approach to hardware design based on a many-coremicroarchitectural template used to implement compute-bound applications expressed in a high-level data-parallel language such as OpenCL. The template is customized on a per-...
- articleJanuary 2012
A hardware-accelerated ECDLP with high-performance modular multiplication
International Journal of Reconfigurable Computing (IJRC), Volume 2012Article No.: 7, Page 7https://doi.org/10.1155/2012/439021Elliptic curve cryptography (ECC) has become a popular public key cryptography standard. The security of ECC is due to the difficulty of solving the elliptic curve discrete logarithm problem (ECDLP). In this paper, we demonstrate a successful attack on ...
- articleJanuary 2012
Object recognition and pose estimation on embedded hardware: SURF-based system designs accelerated by FPGA logic
International Journal of Reconfigurable Computing (IJRC), Volume 2012Article No.: 6, Page 6https://doi.org/10.1155/2012/368351State-of-the-art object recognition and pose estimation systems often utilize point feature algorithms, which in turn usually require the computing power of conventional PC hardware. In this paper, we describe two embedded systems for object detection ...