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- research-articleJune 2024
Quantum Support Vector Machine for Classifying Noisy Data
IEEE Transactions on Computers (ITCO), Volume 73, Issue 9Pages 2233–2247https://doi.org/10.1109/TC.2024.3416619Noisy data is ubiquitous in quantum computer, greatly affecting the performance of various algorithms. However, existing quantum support vector machine models are not equipped with anti-noise ability, and often deliver low performance when learning ...
- research-articleMay 2008
A Serial Memory by Quantum-Dot Cellular Automata (QCA)
IEEE Transactions on Computers (ITCO), Volume 57, Issue 5Pages 606–618https://doi.org/10.1109/TC.2007.70831Quantum-dot Cellular Automata (QCA) has been widely advocated as a new device architecture for nano technology. QCA systems require extremely low power together with the potential for high density andregularity. These features make QCA an attractive ...
- research-articleFebruary 2007
Neural Network Simulation and Evolutionary Synthesis of QCA Circuits
IEEE Transactions on Computers (ITCO), Volume 56, Issue 2Pages 191–201https://doi.org/10.1109/TC.2007.33CMOS technology miniaturization limits have promoted research on new alternatives which can keep the technologically advanced level of the last decades. Quantum-dot Cellular Automata (QCA) is a new technology in the nanometer scale that has been ...
- research-articleFebruary 2007
Hierarchical Probabilistic Macromodeling for QCA Circuits
IEEE Transactions on Computers (ITCO), Volume 56, Issue 2Pages 174–190https://doi.org/10.1109/TC.2007.30With the goal of building an hierarchical design methodology for quantum-dot cellular automata (QCA) circuits, we put forward a novel, theoretically sound, method for abstracting the behavior of circuit components in QCA circuit, such as majority logic, ...
- research-articleMarch 2005
Addition Related Arithmetic Operations via Controlled Transport of Charge
IEEE Transactions on Computers (ITCO), Volume 54, Issue 3Pages 243–256https://doi.org/10.1109/TC.2005.40This paper investigates the Single Electron Tunneling (SET) technology-based computation of basic addition related arithmetic functions, e.g., addition and multiplication, via a novel computation paradigm, which we refer to as electron counting ...
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- research-articleAugust 2004
Universal delay-insensitive circuits with bidirectional and buffering lines
IEEE Transactions on Computers (ITCO), Volume 53, Issue 8Pages 1034–1046https://doi.org/10.1109/TC.2004.51Delay-insensitive (DI) circuits are a class of asynchronous circuits whose correctness of operation is robust to arbitrary delays in modules or interconnection lines. Keller clarified the precise operating conditions of the class of DI-circuits and ...
- research-articleOctober 2000
On the Generation of High-Quality Random Numbers by Two-Dimensional Cellular Automata
IEEE Transactions on Computers (ITCO), Volume 49, Issue 10Pages 1146–1151https://doi.org/10.1109/12.888056Finding good random number generators (RNGs) is a hard problem that is of crucial import in several fields, ranging from large-scale statistical physics simulations to hardware self-test. In this paper, we employ the cellular programming evolutionary ...
- research-articleMarch 1999
2-by-n$n$ Hybrid Cellular Automata with Regular Configuration: Theory and Application
IEEE Transactions on Computers (ITCO), Volume 48, Issue 3Pages 285–295https://doi.org/10.1109/12.754995This paper introduces a new class of two-dimensional linear cellular automata and derives a number of their properties. A recursive relation is proved which enables the characteristic polynomial to be efficiently calculated, and minimal cost, maximal ...
- research-articleAugust 1998
Cellular-Automata-Array-Based Diagnosis of Board Level Faults
IEEE Transactions on Computers (ITCO), Volume 47, Issue 8Pages 817–828https://doi.org/10.1109/12.707584A novel scheme for board level fault diagnosis based on Cellular Automata Array (CAA) is presented. In the proposed diagnosis scheme, the output responses of the chips are encoded by applying the strategy of CA-based byte error correcting code [1], [2]. ...
- research-articleNovember 1997
Cellular Automata for Weighted Random Pattern Generation
IEEE Transactions on Computers (ITCO), Volume 46, Issue 11Pages 1219–1229https://doi.org/10.1109/12.644297Fault testing random-pattern-resistant circuits requires that BIST (built-in self-test) techniques generate large numbers of pseudorandom patterns. To shorten these long test lengths, this study describes a cellular automata-based method that ...
- research-articleMay 1997
Reply to Comments on "Theory and Application of Cellular Automata in Cryptography"
IEEE Transactions on Computers (ITCO), Volume 46, Issue 5Page 639https://doi.org/10.1109/TC.1997.589246This reply emphasizes the point that the regular, modular, cascadable structure of local neighborhood CA can be employed for building low cost cipher system hardware. This cost effective engineering solution can achieve desired level of security with ...
- research-articleMay 1997
Comments on "Theory and Applications of Cellular Automata in Cryptography"
IEEE Transactions on Computers (ITCO), Volume 46, Issue 5Pages 637–638https://doi.org/10.1109/12.589245The cipher systems based on Cellular Automata proposed by Nandi et al. [3] are affine and are insecure.
- research-articleSeptember 1996
CAA Decoder for Cellular Automata Based Byte Error Correcting Code
IEEE Transactions on Computers (ITCO), Volume 45, Issue 9Pages 1003–1016https://doi.org/10.1109/12.537123Design of Cellular Automata (CA) based byte error correcting code analogous to extended Reed-Solomon code has been proposed in [1], [2]. This code has same restrictions on error correction as that of extended R-S code. In this paper a new design scheme ...
- research-articleJuly 1996
Analysis of One-Dimensional Linear Hybrid Cellular Automata over GF(q)
IEEE Transactions on Computers (ITCO), Volume 45, Issue 7Pages 782–792https://doi.org/10.1109/12.508317This paper studies theoretical aspects of one-dimensional linear hybrid cellular automata over a finite (Galois) field. General results concerning the characteristic polynomials of such automata are presented. A probabilistic synthesis algorithm for ...
- research-articleJuly 1996
Theory and Application of Nongroup Cellular Automata for Synthesis of Easily Testable Finite State Machines
IEEE Transactions on Computers (ITCO), Volume 45, Issue 7Pages 769–781https://doi.org/10.1109/12.508316This paper reports some of the interesting properties and relationships of a nongroup Cellular Automata (CA) and its dual. A special class of nongroup Cellular Automata denoted as D1*CA is analytically investigated. Based on such analysis, D1*CA has ...
- research-articleMarch 1996
BIST Test Pattern Generators for Two-Pattern Testing-Theory and Design Algorithms
IEEE Transactions on Computers (ITCO), Volume 45, Issue 3Pages 257–269https://doi.org/10.1109/12.485565Testing for delay and CMOS stuck-open faults requires two-pattern tests, and typically a large number of two pattern tests are needed. Built-in self-test (BIST) schemes are attractive for comprehensive testing of such faults. BIST test pattern ...
- research-articleJanuary 1996
Analysis of Periodic and Intermediate Boundary 90/150 Cellular Automata
IEEE Transactions on Computers (ITCO), Volume 45, Issue 1Pages 1–12https://doi.org/10.1109/12.481481Considerable interest has been recently generated in the study of Cellular Automata (CA) behavior. Polynomial and matrix algebraic tools are employed to characterize some of the properties of null/periodic boundary CA. Some other results of group CA ...
- research-articleOctober 1995
A Low-Cost High-Capacity Associative Memory Design Using Cellular Automata
IEEE Transactions on Computers (ITCO), Volume 44, Issue 10Pages 1260–1264https://doi.org/10.1109/12.467703The present paper reports a novel scheme for designing fast retrieval memory system using cellular automata. In essence, the proposed scheme implements the concept of hashing in hardware. This makes possible the design of low-cost high-capacity memory ...
- research-articleAugust 1995
Complete Decomposition of Stochastic Petri Nets Representing Generalized Service Networks
IEEE Transactions on Computers (ITCO), Volume 44, Issue 8Pages 1031–1046https://doi.org/10.1109/12.403719Complete decomposition is a new strategy for evaluating the performance of a network of generalized service centers, represented in the notation of Generalized Stochastic Petri Nets (GSPNs). Each service center can have arbitrary internal structure (...
- research-articleJune 1995
A Deterministic Built-In Self-Test Generator Based on Cellular Automata Structures
IEEE Transactions on Computers (ITCO), Volume 44, Issue 6Pages 805–816https://doi.org/10.1109/12.391181This paper proposes a new approach for designing a cost-effective, on-chip, deterministic, built-in, self-test generator. Given a set of precomputed test vectors (obtained by an ATPG tool) with a predetermined fault coverage, a simple test vector ...