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- ArticleJanuary 2005
A domain specific reconfigurable Viterbi fabric for system-on-chip applications
ASP-DAC '05: Proceedings of the 2005 Asia and South Pacific Design Automation ConferencePages 916–919https://doi.org/10.1145/1120725.1121069A novel embedded dynamically reconfigurable fabric for implementing the Viterbi algorithm in a System-on-Chip device is presented in this paper. The proposed reconfigurable fabric can support Viterbi implementations for different standards, such as GSM, ...
- ArticleJanuary 2005
A function generator-based reconfigurable system
ASP-DAC '05: Proceedings of the 2005 Asia and South Pacific Design Automation ConferencePages 905–909https://doi.org/10.1145/1120725.1121067This paper proposes a new reconfigurable system which has a function generator-based CLB architecture. This is different from the standard look-up table (LUT) based CLB architectures available in commercial FPGAs. The new function generation ...
- ArticleJanuary 2005
Area-IO DRAM/logic integration with system-in-a-package (SiP)
ASP-DAC '05: Proceedings of the 2005 Asia and South Pacific Design Automation ConferencePages 893–896https://doi.org/10.1145/1120725.1121063This paper presents a cost-effective area-IO DRAM (aDRAM)/Logic integration implemented with CLC (Chip-Laminate-Chip)-based System-in-a-Package (SiP) technology. By inserting 512 area-IOs into the area-IO DRAM, the bandwidth of the area-IO DRAM can ...
- ArticleJanuary 2005
An accurate 1.08-GHz CMOS LC voltage-controlled oscillator
ASP-DAC '05: Proceedings of the 2005 Asia and South Pacific Design Automation ConferencePages 889–892https://doi.org/10.1145/1120725.1121062An accurate 1.08-GHz CMOS LC voltage-controlled oscillator is implemented in a 0.35μm standard 2P4M CMOS process. In this paper we present a new convenient method of calculation of oscillating period. With this period calculation technique, the ...
- ArticleJanuary 2005
An advanced bit-line clamping scheme in magnetic RAM for wide sensing margin
ASP-DAC '05: Proceedings of the 2005 Asia and South Pacific Design Automation ConferencePages 877–882https://doi.org/10.1145/1120725.1121060This paper proposes the bit-line clamping scheme for a stable signal margin in Magnetoresistance RAM. MRAM distinguishes data by the difference of resistance in MTJ. However, there are so many error sources in MTJ that it limits a yield factor. In this ...
- ArticleJanuary 2005
Wake-up protocols for controlling current surges in MTCMOS-based technology
ASP-DAC '05: Proceedings of the 2005 Asia and South Pacific Design Automation ConferencePages 868–871https://doi.org/10.1145/1120725.1121057This paper proposes strategies to control the wake-up noise for circuits implemented in MTCMOS technology. In MTCMOS circuits, during the switchings between the active and standby modes, sudden surges in current happens due to floating voltages at the ...
- ArticleJanuary 2005
Optimal module and voltage assignment for low-power
ASP-DAC '05: Proceedings of the 2005 Asia and South Pacific Design Automation ConferencePages 850–855https://doi.org/10.1145/1120725.1121054Reducing power consumption through high-level synthesis has attracted a growing interest from researchers due to its large potential for power reduction. In this work we study functional unit binding (or module assignment) given a scheduled data flow ...
- ArticleJanuary 2005
A fractional delay-locked loop for on chip clock generation applications
ASP-DAC '05: Proceedings of the 2005 Asia and South Pacific Design Automation ConferencePages 1300–1309https://doi.org/10.1145/1120725.1121048A fractional multiplying delay-locked loop (FMDLL) for high speed on-chip clock generation applications is presented. The proposed DLL architecture overcomes some drawbacks of phase-locked loops (PLLs) such as jitter accumulation and stability while ...
- ArticleJanuary 2005
Reducing leakage power in instruction cache using WDC for embedded processors
ASP-DAC '05: Proceedings of the 2005 Asia and South Pacific Design Automation ConferencePages 1292–1295https://doi.org/10.1145/1120725.1121046Power consumption is an important design issue of current embedded systems and SoC. It has been shown that instruction cache accounts for a significant portion of the power dissipation of the whole processor chip. WDC (Way-Decay Cache) proposed in this ...
- ArticleJanuary 2005
A generalized quadrature bandpass sampling in radio receivers
ASP-DAC '05: Proceedings of the 2005 Asia and South Pacific Design Automation ConferencePages 1288–1291https://doi.org/10.1145/1120725.1121045Bandpass Sampling (BPS) realizes frequency down-conversion by undersampling. Noise aliasing as the direct consequence of the lower sampling rate causes a performance degradation. In this paper, a Generalized Quadrature BPS (GQBPS) combined with a filter ...
