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- research-articleDecember 2024
Modeling and Parasitic Extraction of the MM9 Transistor for GHz/THz CMOS RF Circuit Design
Journal of Electronic Testing: Theory and Applications (JELT), Volume 40, Issue 6Pages 795–804https://doi.org/10.1007/s10836-024-06154-2AbstractThe goal of this paper is to decrease the number of complicated mathematical calculations for extracting the values of parasitic components and to examine the RF behavior of CMOS circuits rapidly by proposing a simple, bias-independent, three-...
- research-articleDecember 2024
Multi-modal Pre-silicon Evaluation of Hardware Masking Styles
Journal of Electronic Testing: Theory and Applications (JELT), Volume 40, Issue 6Pages 723–740https://doi.org/10.1007/s10836-024-06155-1AbstractProtecting sensitive logic functions in ASICs requires side-channel countermeasures. Many gate-level masking styles have been published, each with pros and cons. Some styles such as RSM, GLUT, and ISW are compact but can feature 1st-order leakage. ...
- research-articleDecember 2024
A SLvT Adaptive Test Method for Integrated Circuit Test Parameter Sets without Yield Loss
Journal of Electronic Testing: Theory and Applications (JELT), Volume 40, Issue 6Pages 777–793https://doi.org/10.1007/s10836-024-06152-4AbstractWith the development of semiconductor technology, the fabrication process of integrated circuits is complicated and expensive, and the testing of integrated circuits has become increasingly difficult. The reduction of testing costs has become a ...
- research-articleDecember 2024
A Feature-Adaptive and Scalable Hardware Trojan Detection Framework For Third-party IPs Utilizing Multilevel Feature Analysis and Random Forest
Journal of Electronic Testing: Theory and Applications (JELT), Volume 40, Issue 6Pages 741–759https://doi.org/10.1007/s10836-024-06150-6AbstractThe trustworthiness of integrated circuits is susceptible to the hardware Trojans in the third-party intellectual property (IP) cores. Various hardware Trojan detection approaches have been proposed to identify the Trojans from a given netlist at ...
- research-articleNovember 2024
Advancing Low Power BIST Architecture with GAN-Driven Test Pattern Optimization
Journal of Electronic Testing: Theory and Applications (JELT), Volume 40, Issue 6Pages 691–705https://doi.org/10.1007/s10836-024-06153-3AbstractA novel approach to achieve low power consumption during Built-In Self-Test (BIST) operations in Very Large Scale Integrated (VLSI) circuits through the integration of Generative Adversarial Networks (GANs) in the test pattern generation process ...
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- research-articleNovember 2024
Fatigue Life Based Study of Electronic Package Mounting Locations on Printed Circuit Boards Subjected to Random Vibration Loads
Journal of Electronic Testing: Theory and Applications (JELT), Volume 40, Issue 6Pages 761–776https://doi.org/10.1007/s10836-024-06151-5AbstractPlastic Ball Grid Array (PBGA) packages (chips) mounted on a Printed Circuit Board (PCB) assembly are vulnerable and are more likely to fail when they are subjected to random vibration environmental conditions. The proper positioning of the ...
- announcementNovember 2024
2023 JETTA-TTTC Best Paper Award: Hui Jiang, Fanchen Zhang, Jennifer Dworak, Kundan Nepal, and Theodore Manikas, “Increased Detection of Hard-to-Detect Stuck-at Faults during Scan Shift,” Journal of Electronic Testing: Theory and Applications, Volume 39, Number 2, pp. 227–243, April 2023
Journal of Electronic Testing: Theory and Applications (JELT), Volume 40, Issue 5Pages 591–593https://doi.org/10.1007/s10836-024-06147-1AbstractTest sets that target standard fault models may not always be sufficient for detecting all defects. To evaluate test sets for the detection of unmodeled defects, n-detect test sets (which detect all modeled faults at least n times) have previously ...
- research-articleNovember 2024
YOLOv8-TDD: An Optimized YOLOv8 Algorithm for Targeted Defect Detection in Printed Circuit Boards
Journal of Electronic Testing: Theory and Applications (JELT), Volume 40, Issue 5Pages 645–656https://doi.org/10.1007/s10836-024-06146-2AbstractAn enhanced approach for detecting defects in Printed Circuit Boards (PCBs) using a significantly improved version of the YOLOv8 algorithm is proposed in this research, the proposed method is referred to as YOLOv8-TDD (You Only Look Once Version8-...
- research-articleOctober 2024
Test Modules for Enhanced Testability of Single Flux Quantum Integrated Circuits
Journal of Electronic Testing: Theory and Applications (JELT), Volume 40, Issue 5Pages 595–602https://doi.org/10.1007/s10836-024-06141-7AbstractOn-chip testability of superconductive electronic circuits is challenging due to the high clock frequencies and cryogenic environment, which in turn complicates the test/debug process. In this paper, circuit solutions to support design for ...
- research-articleOctober 2024
Reliability Analysis for a GaAs LNA with Temperature Stress
Journal of Electronic Testing: Theory and Applications (JELT), Volume 40, Issue 5Pages 679–687https://doi.org/10.1007/s10836-024-06144-4AbstractIn order to investigate the reliability of gallium arsenide (GaAs) monolithic microwave integrated circuit (MMIC) low noise amplifier (LNA), a series of tests have been carried out here. The results show that with the rising temperature the small-...
- research-articleOctober 2024
PCB Defect Recognition by Image Analysis using Deep Convolutional Neural Network
Journal of Electronic Testing: Theory and Applications (JELT), Volume 40, Issue 5Pages 657–667https://doi.org/10.1007/s10836-024-06145-3AbstractPrinted circuit board (PCB) is one of the most important components of electronic products. The traditional defect detection methods are very difficult to meet the defect detection requirements in the PCB production process. In recent years, the ...
- research-articleOctober 2024
Generating Synthetic Layout Test Patterns using Deep Learning
Journal of Electronic Testing: Theory and Applications (JELT), Volume 40, Issue 5Pages 603–614https://doi.org/10.1007/s10836-024-06138-2AbstractThe testing process of various electronic design automation tools and the verification process of the manufacturability of a developed Design Rule Check (DRC) deck, particularly in very-large-scale integration designs, is highly dependent on the ...
- research-articleOctober 2024
Equivalent Circuit and Damage Threshold Study of Communication Interfaces under HEMP
Journal of Electronic Testing: Theory and Applications (JELT), Volume 40, Issue 5Pages 615–624https://doi.org/10.1007/s10836-024-06140-8AbstractIn a strong electromagnetic pulse environment, high-intensity, broadband electromagnetic pulse energy is transmitted to the communication interface circuit through the interconnection cable, causing interference or damage to the internal ...
- research-articleOctober 2024
Investigating and Improving the Performance of Radiation-Hardened SRAM Cell with the Use of Multi-Voltage Transistors
Journal of Electronic Testing: Theory and Applications (JELT), Volume 40, Issue 5Pages 625–644https://doi.org/10.1007/s10836-024-06143-5AbstractThis research introduces a proposed energy-efficient radiation-hardened and improved read stability (RHIRS)-12T SRAM cell with a polarity hardening technique, which lowers the vulnerable nodes and allows all single-event upset (SEU) techniques to ...
- research-articleOctober 2024
A Defect Detection Method of Mixed Wafer Map Using Neighborhood Path Filtering Clustering Algorithm
Journal of Electronic Testing: Theory and Applications (JELT), Volume 40, Issue 4Pages 419–433https://doi.org/10.1007/s10836-024-06132-8AbstractAs the wafer process becomes more complex, the probability of mixed-type defective wafer maps is constantly increasing. Therefore, it is necessary to perform effective filtering and denoising processing on the mixed-type defective wafer map to ...
- research-articleSeptember 2024
Interleaved Counter Matrix Code in SRAM Memories for Continuous Adjacent Multiple Bit Upset Correction
Journal of Electronic Testing: Theory and Applications (JELT), Volume 40, Issue 4Pages 525–537https://doi.org/10.1007/s10836-024-06135-5AbstractSRAM memory systems are suffering from an increase in data due to the aggressive CMOS integration density. The frequency of Multiple Cell Upsets (MCUs) on SRAM memory is increasing, which is resulting in the increasing use of ECCs.Speed is slowed ...
- research-articleSeptember 2024
High-Dimensional Feature Fault Diagnosis Method Based on HEFS-LGBM
Journal of Electronic Testing: Theory and Applications (JELT), Volume 40, Issue 4Pages 557–572https://doi.org/10.1007/s10836-024-06134-6AbstractThe challenge caused by redundant feature interference in high-dimensional fault feature data of analog circuits, will undermines the efficacy of conventional analog circuit fault diagnosis techniques, Thus, a novel approach termed Heterogeneous ...
- research-articleSeptember 2024
Pebble Traversal-Based Fault Detection and Advanced Reconfiguration Technique for Digital Microfluidic Biochips
Journal of Electronic Testing: Theory and Applications (JELT), Volume 40, Issue 4Pages 573–587https://doi.org/10.1007/s10836-024-06137-3AbstractDigital Microfluidic Biochips (DMFBs) are rapidly replacing conventional biomedical analyzers by incorporating diverse bioassay operations with better throughput and precision at a negligible cost. In the last decade, these microfluidic devices ...
- research-articleAugust 2024
Predicting Energy Dissipation in QCA-Based Layered-T Gates Under Cell Defects and Polarisation: A Study with Machine-Learning Models
Journal of Electronic Testing: Theory and Applications (JELT), Volume 40, Issue 4Pages 435–455https://doi.org/10.1007/s10836-024-06133-7AbstractThe semiconductor industry has encountered the physical constraints of current semiconductor materials and the impending end of Moore's forecast. The recent edition of the International Roadmap for Devices and Systems reveals that the ...