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(2007). Congestion Optimization During Technology Mapping and Logic Synthesis. In: Routing Congestion in VLSI Circuits: Estimation and Optimization. Series on Integrated Circuits and Systems. Springer, Boston, MA. https://doi.org/10.1007/0-387-48550-3_6
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DOI: https://doi.org/10.1007/0-387-48550-3_6
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