Reconfigurable Systems: Past and Next 10 Years

Abstract

A driving factor in Digital System DS architecture is the feature size of the silicon implementation process. We present Moore’s laws and focus on the shrink laws, which relate chip performance to feature size. The theory is backed with experimental measures from [14], relating performance to feature size, for various memory, processor and FPGA chips from the past decade. Conceptually shrinking back existing chips to a common feature size leads to common architectural measures, which we call normalised: area, clock frequency, memory and operations per cycle. We measure and compare the normalised compute density of various chips, architectures and silicon technologies.

A Reconfigurable System RS is a standard processor tightly coupled to a Programmable Active Memory PAM, through a high bandwidth digital link. The PAM is a FPGA and SRAM based coprocessor. Through software configuration, it may emulate any specific custom hardware, within size and speed limits. RS combine the flexibility of software programming to the performance level of application specific integrated circuits ASIC. We analyse the performance achieved by P1, a first generation RS [13]. It still holds some significant absolute speed records: RSA cryptography, applications from high-energy physics, and solving the Heat Equation. We observe how the software versions for these applications have gained performance, through better microprocessors. We compare with the performance gain which can be achieved, through implementation in P2, a second-generation RS [16].

Recent experimental systems, such as the Dynamically Programmable Arithmetic Array in [19] and others in [14], present advantages over current FPGA, both in storage and compute density. RS based on such chips are tailored for video processing, and similar compute, memory and IO bandwidth intensive. We characterise some of the architectural features that a RS must posses in order to be fit to shrink: automatically enjoy the optimal gain in performance through future shrinks. The key to scale, for any general purpose system, is to embed memory, computation and communication at a much deeper level than presently done.

This research was partly done at Hewlett Packard Laboratories, Bristol U.K.