Abstract
Violations in the timing constraints of a clocked register can cause a synchronous system to malfunction. The effects of parameter variations on the timing characteristics of registers that determine the timing constraints are investigated in this paper. The sensitivity of the setup time and data propagation delay to parameter variations is demonstrated for four different register designs. The robustness of each register design under variations in power supply voltage, temperature, and gate oxide thickness is determined.
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Roberts, W.R., Velenis, D. (2005). Parameter Variation Effects on Timing Characteristics of High Performance Clocked Registers. In: Paliouras, V., Vounckx, J., Verkest, D. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2005. Lecture Notes in Computer Science, vol 3728. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11556930_52
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DOI: https://doi.org/10.1007/11556930_52
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-29013-1
Online ISBN: 978-3-540-32080-7
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