Keynote 2: The Chip-Multiprocessing Paradigm Shift: Opportunities and Challenges

Abstract

At a point in time when it is harder to harvest more instruction-level parallelism and to push the clock frequency to higher levels, industry has opted for integrating multiple processor cores on a chip. It is an attractive way of reducing the verification time by simply replicating moderately complex cores on a chip, but it introduces several challenges. The first challenge is to transform the processing power of multiple cores to application parallelism. The second challenge is to bridge the increasing speedgap between processor and memory by more elaborate on-chip memory hierarchies. Related to the second challenge is how to make more effective use of the limited bandwidth out of and into the chip.

In this talk I will elaborate on the opportunities that chipmultiprocessing offers but also the research issues that it introduces. Even if multiprocessing has been studied for more than two decades, the tight integration of cores and their on-chip memory subsystems opens up new unexplored terrains. I will discuss approaches to explore new forms of parallelism, approaches to bridge the processor/memory speedgap. In particular, I will focus on approaches to improve the way we utilize processor and memory resources. I will exemplify with approaches being studied in my own research as well as elsewhere. Finally, I will present an outlook of why I believe that parallel processing is one of the main hopes for the future of computer architecture and related fields, e.g. compilers.