Abstract
The development of more and more complex embedded systems constitutes a very challenging task for EDA experts, due to their HW/SW-mixed nature joint to the high demand for quality and reliability. Recently, both industrial engineers and academic researchers have developed a very large number of techniques for dynamic verification in terms of co-simulation, which, in particular, address the different nature of hardware and software components of an embedded system. However, a widely accepted methodology does not exist. Thus, this paper is intended to provide a general view on simulation-based modeling and verification strategies for developing embedded systems. In particular, the paper is focussed on describing state-of-the art co-simulation approaches and verification strategies based on fault simulation and assertion checking.
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Bombieri, N., Fummi, F., Pravadelli, G. (2006). Hardware Design and Simulation for Verification. In: Bernardo, M., Cimatti, A. (eds) Formal Methods for Hardware Verification. SFM 2006. Lecture Notes in Computer Science, vol 3965. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11757283_1
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DOI: https://doi.org/10.1007/11757283_1
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