Abstract
The manufacturing defect in the interconnect lines can lead to various electrical faults, e.g. defect due to under-etching effect/conductive particle contamination on interconnect line can lead to increased coupling capacitances between the two adjacent interconnects, which, in turn, can eventually result in crosstalk fault in the DSM chips. In this paper we describe the line defect-based-crosstalk fault model that will be helpful in analyzing the severity of the defect/fault, as the crosstalk fault occasionally leads to various signal integrity losses, such as timing violation due to excessive signal delay or speed-up, logic failure due to crosstalk positive/negative glitch above/below logic low/high threshold and also reliability problem particularly due to crosstalk glitch above logic high threshold. Our crosstalk fault model accuracy is very close to PSPICE simulation results when the defect/fault is located in the middle of interconnects, whereas for the defects located at the near-end/far-end side of aggressor-victim the model accuracy differs approximately by ±5% respectively.
CMOS12 technology data provided by Philips Semiconductors GmbH, DTC, Hamburg, Germany.
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References
Arumi, D., Rodriguez-Montanes, R., Figueras, J.: Defective behaviours of Resistive opens in interconnect line. In: Proc. of IEEE-ETS 2005, pp. 28–33 (2005)
Chen, G., Reddy, S., Pomeranz, I., Rajaski, J., Engelke, P., Becker, B.: An unified Fault model and Test generation procedure for interconnect opens and bridges. In: Proc. of IEEE-ETS 2005, pp. 22–27 (2005)
Cuviello, M., Dey, S., Bai, X., Zhao, Y.: Fault Modeling and Simulation for Crosstalk in System-on-Chip Interconnects. In: Proc. of ICCAD 1999, pp. 297–303 (1999)
Palit, A.K., Anheier, W., Schloeffel, J.: Estimation of Signal Integrity Loss through Reduced Order Interconnect Model. In: Proc. IEEE-SPI 2003, Siena, Italy, pp. 163–166 (2003)
Palit, A.K., Wu, L., Duganapalli, K.K., Anheier, W., Schloeffel, J.: A new, flexible and very accurate crosstalk fault model to analyze the effects of coupling noise between the interconnects on signal integrity losses in deep submicron chips, paper no. 253. In: Proc. of 14th IEEE-ATS 2005, Calcutta, India, December 18-21, 2005, pp. 22–26 (2005)
Young, B.: Digital signal integrity: modeling and simulations with interconnects and packages, pp. 98–101. Prentice Hall PTR, Upper Saddle River, New Jersey (2001)
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© 2006 Springer-Verlag Berlin Heidelberg
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Palit, A.K., Duganapalli, K.K., Anheier, W. (2006). Modeling of Crosstalk Fault in Defective Interconnects. In: Vounckx, J., Azemard, N., Maurine, P. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2006. Lecture Notes in Computer Science, vol 4148. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11847083_33
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DOI: https://doi.org/10.1007/11847083_33
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