Abstract
The high performance cryptographic chip is the core unit of the network information safety equipments. This paper proposes the design approach of the AES cryptographic system based on reconfigurable hardware, develops the method of key-sequence generation with the genetic algorithm that realizes different cipher key in every encryption round. The system has been implemented on Virtex-E FPGA. The result proves that the new design technology is feasible, and the security level of the AES is improved.
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© 2006 Springer-Verlag Berlin Heidelberg
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Wang, L., Wang, Y., Yao, R., Zhang, Z. (2006). Hardware Implementation of AES Based on Genetic Algorithm. In: Jiao, L., Wang, L., Gao, X., Liu, J., Wu, F. (eds) Advances in Natural Computation. ICNC 2006. Lecture Notes in Computer Science, vol 4222. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11881223_115
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DOI: https://doi.org/10.1007/11881223_115
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-45907-1
Online ISBN: 978-3-540-45909-5
eBook Packages: Computer ScienceComputer Science (R0)