Abstract
This paper discusses the design and implementation of a profile-based power-aware compiler using dynamic voltage scaling. The compiler identifies program regions where the CPU can be slowed down without resulting in a significant overall performance loss. Two strategies have been implemented in SUIF2. The single-region strategy slows down a single region for energy savings, while the multiple-region strategy slows down as many regions as needed. A comparison of both strategies based on six SPECfp95 benchmarks shows that in five cases, the energy-delay product was comparable. In the remaining case, the multiple-region strategy was significantly better. Both strategies achieved energy savings of up to 48% for the five programs at the slowdown between 1% and 16%, and energy savings of 74% for the multiple regions vs. 50% for the single region strategy for the remaining program at the slowdown up to 21%.
This research was partially supported by NSF CAREER award CCR-9985050.
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Hsu, CH., Kremer, U. (2003). Single Region vs. Multiple Regions: A Comparison of Different Compiler-Directed Dynamic Voltage Scheduling Approaches. In: Falsafi, B., Vijaykumar, T.N. (eds) Power-Aware Computer Systems. PACS 2002. Lecture Notes in Computer Science, vol 2325. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-36612-1_13
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