Abstract
In this paper we present a new design flow for efficient hardware implementation of behavioral system specifications at algorithmic level into heterogeneous multi-FPGA (Field-Programmable Gate Arrays) rapid prototyping systems. We discuss the benefits of coupling the high-level synthesis tool CADDY-II and the partitioning and mapping environment PUMA, which is designed for optimized implementation of RT-level (Register-Transfer) netlists into multi-FPGA architectures. With our new approach, rapid prototyping and in-circuit verification in earliest design phases are enabled. Due to short implementation times and precise back annotation accomplished by a close coupling of the tools, more design iterations and thus better design space exploration is possible.
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Harbich, K., Barke, E. (2001). PuMA++: From Behavioral Specification to Multi-FPGA-Prototype. In: Brebner, G., Woods, R. (eds) Field-Programmable Logic and Applications. FPL 2001. Lecture Notes in Computer Science, vol 2147. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-44687-7_14
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DOI: https://doi.org/10.1007/3-540-44687-7_14
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