Abstract
The problem of reconfiguring a two-dimensional degradable VLSI/WSI array under the row and column routing constraints is NP-complete. This paper aims to decrease gate delay and increase the harvest. A new architecture with six-port switches is proposed. New greedy rerouting algorithms and new compensation approaches are presented and used to reform the reconfiguration algorithm. Experimental results show that the new reconfiguration algorithm consistently outperforms the latest algorithm, both in terms of the percentages of harvest and that of degradation of VLSI/WSI array.
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© 2002 Springer-Verlag Berlin Heidelberg
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Jigang, W., Schröder, H., Thambipillai, S. (2002). New Architecture and Algorithms for Degradable VLSI/WSI Arrays. In: Ibarra, O.H., Zhang, L. (eds) Computing and Combinatorics. COCOON 2002. Lecture Notes in Computer Science, vol 2387. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-45655-4_21
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DOI: https://doi.org/10.1007/3-540-45655-4_21
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