Abstract
Dual supply voltage scaling (DSVS) is an emerging technique in logic-level power optimization. In this paper, a novel design methodology, which enables DSVS to be carried out in a state-of-the-art environment for power-driven logic synthesis, is presented. The idea is to provide a dual supply voltage standard cell library modeled such that a typical gate sizing algorithm can be exploited for DSVS. Since this approach renders dedicated DSVS algorithms superfluous, only little modification of established design flows is required. The methodology has been applied to MCNC benchmark circuits. Compared to the results of single supply voltage power-driven logic synthesis, additional power reductions of 10% on average and 24% in the best case have been achieved.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
B. Ackalloor and D. Gaitonde, “An overview of library characterization in semicustom design,” IEEE Custom Integrated Circuits Conf., pp. 305–312, 1998.
C. Chen, A. Srivastava, and M. Sarrafzadeh, “On gate level power optimization using dual-supply voltages,” IEEE Trans. on VLSI Systems, vol. 9, pp. 616–629, Dec. 2001.
O. Coudert, “Gate sizing for constrained delay/power/area optimization,” IEEE Trans. on VLSI Systems, vol. 5, pp. 465–472, Dec. 1997.
T. Mahnke et al., “Power optimization through dual supply voltage scaling using Power Compiler,” Proc. European Synopsys Users Group Meeting, 2002.
LGSynth93, Benchmark set used in conjunction with 1993 MCNC International Workshop on Logic Synthesis, http://www.cbl.ncsu.edu, June 2002.
Synopsys Inc., “Design power and power compiler technology backgrounder,” Jan. 1998, http://www.synopsys.com/products/power/power bkg.html, July 2001.
K. Usami and M. Horowitz, “Clustered voltage scaling technique for low-power design,” Proc. Int. Symp. on Low-Power Design, pp. 3–8, 1995.
K. Usami et al., “Automated low-power technique exploiting multiple supply voltages applied to a media processor,” IEEE Journal of Solid-State Circuits, vol. 33, pp. 463–472, March 1998.
K. Usami et al., “Design methodology of ultra low-power MPEG4 codec core exploiting voltage scaling techniques,” Proc. 35th DAC, pp. 483–488, 1998.
C. Yeh et al., “Gate-level design exploiting dual supply voltages for power-driven applications,” Proc. 36th DAC, pp. 68–71, 1999.
C. Yeh et al., “Layout techniques supporting the use of dual supply voltages for cell-based designs,” Proc. 36th DAC, pp. 62–67, 1999.
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2002 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Mahnke, T., Stechele, W., Hoeld, W. (2002). Dual Supply Voltage Scaling in a Conventional Power-Driven Logic Synthesis Environment. In: Hochet, B., Acosta, A.J., Bellido, M.J. (eds) Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2002. Lecture Notes in Computer Science, vol 2451. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-45716-X_15
Download citation
DOI: https://doi.org/10.1007/3-540-45716-X_15
Published:
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-44143-4
Online ISBN: 978-3-540-45716-9
eBook Packages: Springer Book Archive