Abstract
The switching behaviour and the operating region of a complementary metal-oxide-semiconductor (CMOS) gate driving a resistance- inductance-capacitance (RLC) transmission line is investigated in this paper. Closed form expressions for the time the transistors operate in the saturation and triode region respectively are proposed. Closed form expressions show predictions within 10% of HSPICE results for a wide range of line and buffer parameters, making them suitable to be applied to the problem of buffer sizing, repeater insertion, short circuit power estimation and generally whenever the accurate knowledge of the operation of CMOS buffers driving a transmission line is required. In the paper useful hints for choosing the most appropriate model for the triode region of the transistors of the inductive-line driver are also given.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Deutsch A., Koposay G. V., Surovic C. W., Rubin B. J., Terman L. M., Dunne R. P. Jr., Gallo T. A., Dennard R. H.: Modeling and Characterization of Long on Chip Interconnections for High Performance Microprocessors. IBM Journal Res. Dev., Vol 39, n. 5, (1995) 547–567
Ismail Y. I., Friedman E. G., Neves J. L.: Dynamic and Short-Circuit Power of CMOS Gates Driving Lossless Transmission Lines. IEEE trans. On Circuit and Systems-I: Fund. Theory and Applications, Vol. 46, n. 8 (1999) 950–961
Restle, P. J., Jenkins, K. A., Deutsch, A., Cook P. W.: Measurament and Modelling of On-Chip Transmission Line Effects in a 400 MHz Microprocessor. IEEE Journal of Solid-State Circuits, Vol. 33, n. 4 (1998) 662–665
Millman, J., Grabel, A.: Microelectronics. 2nd edn. McGraw-Hill, New York (1987)
Sakurai, T., Newton A. R.: Alpha-Power Law MOSFET Model and its Applications to CMOS Inverter Delay and Other Formulas. IEEE Journal of Solid-State Circuits, Vol. 25, n. 2 (1990) 584–593
Cappuccino, G., Cocorullo, G.: Time-domain Macromodel for Lossy VLSI Interconnect. IEE Electronics Letters, vol. 36, N. 14 (2000) 1207–1208
Bakoglu, H.B.: Circuits, Interconnections and Packaging for VLSI. Addison-Wesley, Reading, Massachusetts (1990)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2002 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Cappuccino, G., Cocorullo, G. (2002). Operating Region Modelling and Timing Analysis of CMOS Gates Driving Transmission Lines. In: Hochet, B., Acosta, A.J., Bellido, M.J. (eds) Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2002. Lecture Notes in Computer Science, vol 2451. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-45716-X_44
Download citation
DOI: https://doi.org/10.1007/3-540-45716-X_44
Published:
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-44143-4
Online ISBN: 978-3-540-45716-9
eBook Packages: Springer Book Archive