Abstract
In this paper a simple analytical model which evaluate the propagation delay of a first-order circuit with a linear input is presented. The model can be used to estimate the propagation delay both of current mode logic (CML) and source coupled logic (SCL) circuits and wires in a VLSI process. The approximation gives an error lower than 6%, and it is a continuous function. The model compared with an ideal RC circuit is successively adopted in a real case such as a CML gate. In particular, this gate was designed with a 6-GHz technology and Spice simulations are performed showing an error lower than 5% in excellent agreement with the theoretical results.
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Mita, R., Palumbo, G. (2002). Modeling of Propagation Delay of a First Order Circuit with a Ramp Input. In: Hochet, B., Acosta, A.J., Bellido, M.J. (eds) Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2002. Lecture Notes in Computer Science, vol 2451. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-45716-X_47
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DOI: https://doi.org/10.1007/3-540-45716-X_47
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