Abstract
It is well-known that the main disadvantages associated with reconfigurable hardware are long reconfiguration latencies, high opcode space requirements, and complex decoder hardware. To overcome these disadvantages, we use microcode since it allows emulation of “complex” operations which are performed using a sequence of smaller and simpler operations. Microcode is used to control the reconfiguration of the reconfigurable hardware, either online or off-line, and the execution on the reconfigurable hardware. Due to the multitude of microcodes and their sizes, it is not feasible to provide on-chip storage for all microcodes. Consequently, the loading of microcode into a limited on-chip storage facility is becoming increasingly more important. In this paper, we present two methods of loading microcodes into such an on-chip storage facility.
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Wong, S., Vassiliadis, S., Cotofana, S. (2002). Microcoded Reconfigurable Embedded Processors: Current Developments. In: Deprettere, E.F., Teich, J., Vassiliadis, S. (eds) Embedded Processor Design Challenges. SAMOS 2001. Lecture Notes in Computer Science, vol 2268. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-45874-3_12
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DOI: https://doi.org/10.1007/3-540-45874-3_12
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