Abstract
We show that the selection of the set of target path delay faults for a sequential subcircuit of a LUT-based FPGA is much more difficult, both conceptually and computationally, than it appears. An essential part of this problem is the identification of the set of irredundant logical paths, i.e. paths whose faults may affect the performance of the FPGA. We develop a classification of logical paths in a sequential subcircuit of a LUT-based FPGA that shows the relationship between irredundant logical paths and other types of logical paths. Based on this classification, we propose several ideas on how to define the set of target path delay faults, so that to allow the test designer to trade-off accuracy and computational complexity when evaluating the circuit testability or the quality of a particular test procedure.
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Krasniewski, A. (2002). On the Set of Target Path Delay Faults in Sequential Subcircuits of LUT-based FPGAs. In: Glesner, M., Zipf, P., Renovell, M. (eds) Field-Programmable Logic and Applications: Reconfigurable Computing Is Going Mainstream. FPL 2002. Lecture Notes in Computer Science, vol 2438. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-46117-5_62
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DOI: https://doi.org/10.1007/3-540-46117-5_62
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