Abstract
We propose a new methodology for exploiting abstraction in the context of model-checking. Our new technique uses abstract BDDs as its underlying data structure. We show that this technique builds a more refined model than traditional compiler-based methods proposed by Clarke, Grumberg and Long. We also provide experimental results to demonstrate the usefulness of our method. We have verified a pipelined carry-save multiplier and a simple version of the PCI local bus protocol. Our verification of the PCI bus revealed a subtle inconsistency in the PCI standard. We believe this is an interesting result by itself.
This research is sponsored by the Semiconductor Research Corporation (SRC) under Contract No. 97-DJ-294 and the National Science Foundation (NSF) under Grant No. CCR-9505472. Any opinions, findings and conclusions or recommendations expressed in this material are those of the authors and do not necessarily reflect the views of SRC, NSF, or the United States Government.
Chapter PDF
Similar content being viewed by others
References
R. E. Bryant, “Graph-Based Algorithms for Boolean Function Manipulation”, IEEE Trans. on Comput., Vol. C-35, No. 8, pp. 677–691, Aug. 1986.
J. R. Burch, E. M. Clarke, D. E. Long, K. L. McMillan, and D. L. Dill, “Symbolic Model Checking for Sequential Circuit Verification”, IEEE Trans. on CAD of Integrated Circuits and System, Vol.13, No.4, pp.401-424, 1994.
E. M. Clarke, E. A. Emerson, and A. P. Sistla, “Automatic verification of finitestate concurrent system using temporal logic”, Proceedings of the Tenth Annual ACM Symposium on Principles of Programming Languages (POPL), January, 1983.
E. M. Clarke, R. Enders, T. Filkorn and S. Jha, “Exploiting Symmetry in Temporal Logic Model Checking”, Formal Methods in System Design 9(1/2):77–104, 1996.
E. M. Clarke and O. Grumberg and H. Hiraishi and S. Jha and D. E. Long and K. L. McMillan and L. A. Ness, “Verification of the Futurebus+ Cache Coherence Protocol”, Formal Methods in System Design 6(2):217–232, 1995.
E. M. Clarke, O. Grumberg, D. E. Long, “Model Checking and Abstraction”, ACM Transactions on Programming Languages and System (TOPLAS), Vol. 16, No. 5, pp. 1512–1542, Sept. 1994.
E. A. Emerson and A. P. Sistla, “Symmetry and Model Checking”, Formal Methods in System Design 9(1/2):105–130, 1996.
P. Godefroid, D. Peled, and M. Staskauskas, “Using Partial Order Methods in the Formal Verification of Industrial Concurrent Programs”, ISSTA'96 International Symposium on Software Testing and Analysis, pp. 261–269, San Diego, California, USA, 1996. ACM Press.
J. L. Hennessy, D. A. Patterson, Computer Architecture: A Quantitative Approach, second edition, 1996. Morgan Kaufman Press.
C. N. Ip and D. L. Dill, “Better Verification Through Symmetry”, Formal Methods in System Design 9(1/2):41–76, 1996.
S. Jha, Y. Lu, M. Minea, E. M. Clarke, “Equivalence Checking using Abstract BDDs”, Intl. Conf. on Computer Design (ICCD), 1997.
Shinji Kimura, “Residue BDD and Its Application to the Verification of Arithmetic Circuits”, 32nd Design Automation Conference (DAC), 1995.
D. E. Long, “Model Checking, Abstraction and Compositional Verification”, School of Computer Science, Carnegie Mellon University publication CMU-CS-93-178, July 1993.
K. L. McMillan, “Symbolic Model Checking: An Approach to the State Explosion Problem”. Kluwer Academic Publishers, 1993.
D. Peled, “Combining Partial Order Reduction with on-the-fly model-checking”, Journal of Formal Methods in System Design, 8(1):39–64.
PCI SGI, “PCI Local Bus Specification”, Production Version Revision 2.1, June 1, 1995.
Kavita Ravi, Abelardo Pardo, Gary D. Hachtel, Fabio Somenzi, “Modular Verification of Multipliers”, Formal Methods in Computer-Aided Design, pp. 49–63, Nov. 1996.
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 1999 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Clarke, E., Jha, S., Lu, Y., Wang, D. (1999). Abstract BDDs: A Technique for Using Abstraction in Model Checking. In: Pierre, L., Kropf, T. (eds) Correct Hardware Design and Verification Methods. CHARME 1999. Lecture Notes in Computer Science, vol 1703. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-48153-2_14
Download citation
DOI: https://doi.org/10.1007/3-540-48153-2_14
Published:
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-66559-5
Online ISBN: 978-3-540-48153-9
eBook Packages: Springer Book Archive