Abstract
We have extended the HOL theorem-prover with an efficient implementation of symbolic trajectory evaluation. Using this extension we can obtain verification results for models of digital hardware — usually with much less effort than would be required using a conventional interactive theorem-proving approach. We illustrate the use of this extension with three examples, namely, the formal verification of a 32-bit adder, an 8-bit by 8-bit multiplier and the MAJORLOGIC block of the Viper microprocessor.
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© 1994 Springer-Verlag Berlin Heidelberg
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Joyce, J., Seger, C. (1994). The HOL-Voss system: Model-checking inside a general-purpose theorem-prover. In: Joyce, J.J., Seger, CJ.H. (eds) Higher Order Logic Theorem Proving and Its Applications. HUG 1993. Lecture Notes in Computer Science, vol 780. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-57826-9_135
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DOI: https://doi.org/10.1007/3-540-57826-9_135
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