Abstract
We present techniques for automating many of the tedious aspects of hardware verification in a higher order logic theorem proving environment. We employ two complementary approaches. The first involves intelligent tactics which incorporate many of the smaller steps currently applied by the user. The second uses hardware combinators to partially automate inductive proofs for iterated hardware structures. We envision a system that captures most of this reasoning in one tactic, SuperDuperHWTac. Ideally, users would use this tactic on a goal for proving that a hardware component meets its specification, and get back a proof documented at a level they would have written by hand. This paper presents preliminary work toward SuperDuperHWTac in both the HOL and Nuprl proof development-systems.
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© 1994 Springer-Verlag Berlin Heidelberg
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Aagaard, M.D., Leeser, M.E., Windley, P.J. (1994). Toward a super duper hardware tactic. In: Joyce, J.J., Seger, CJ.H. (eds) Higher Order Logic Theorem Proving and Its Applications. HUG 1993. Lecture Notes in Computer Science, vol 780. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-57826-9_151
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DOI: https://doi.org/10.1007/3-540-57826-9_151
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