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High level synthesis of synchronous parallel controllers

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Application and Theory of Petri Nets 1996 (ICATPN 1996)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 1091))

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Abstract

In this paper the application of Petri nets to high level synthesis of synchronous parallel controllers is presented. A formal specification of a design is given in a form of an interpreted synchronous Petri net. Behavioral properties of the controller are verified using symbolic traversal of its Petri net model. The net state-space explosion problem is managed using binary decision diagrams (BDDs). Once the Petri net specification of a controller is tested, the BDD representation of the net's state-space is used to generate a state assignment with which the controller can be synthesized. The application of the proposed methodology to the design of a MAXbus port controller for a high performance Transputer Framestore and its comparison to the alternative implementation is discussed. The experimental results clearly demonstrate the advantages of the proposed method. Further, the significant increase of the applicability of this approach has also been achieved.

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Authors and Affiliations

  1. Advanced Computing Research Center, Department of Electrical & Electronic Engineering, University of Bristol, BS8 1TR, Bristol, UK

    Krzysztof Biliński & Erik L. Dagless

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  1. Krzysztof Biliński
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  2. Erik L. Dagless
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Jonathan Billington Wolfgang Reisig

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© 1996 Springer-Verlag Berlin Heidelberg

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Biliński, K., Dagless, E.L. (1996). High level synthesis of synchronous parallel controllers. In: Billington, J., Reisig, W. (eds) Application and Theory of Petri Nets 1996. ICATPN 1996. Lecture Notes in Computer Science, vol 1091. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-61363-3_6

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  • DOI: https://doi.org/10.1007/3-540-61363-3_6

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  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-61363-3

  • Online ISBN: 978-3-540-68505-0

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