Design of dependable hardware: What BIST is most efficient?

Abstract

We show that self-testability is an essential feature of VLSI circuits used as components of dependable systems. We discuss one of the key problems associated with designing self-testable circuits — the selection of BIST (built-in self-test) technique. Specifically, we present advantages and disadvantages of two basic strategies that can be applied when designing a VLSI chip: using one universal BIST technique vs. using several dedicated BIST techniques for a single chip design. As a good candidate for a universal BIST technique, having a potential to effectively and efficiently support the design of a large class of VLSI circuits, we advise the CSTP (Circular Self-Test Path) technique. The applicability of the CSTP is illustrated with an example of self-testable design of a bit-slice processor 2901, a circuit of diversified internal structure comprising various types of functional blocks (ALU, two-port RAM, registers, latches, random logic, multiplexer-based shifters). The design characteristics and the results of simulation experiments carried out for this circuit show that the proposed solution offers high quality testing at acceptable BIST implementation costs.