Joint Hardware / Software Design of a Fast Stream Cipher

Abstract

We explore the problem of designing a stream cipher that is fast in software yet may be efficiently implemented in hardware. We show that a keystream generator built as a word-wide non-linear-feedback shift register can offer both a high degree of parallelism and the hardware simplicity and flexible security of an iterated design. WAKE-ROFB is shown to be an example of this topology. A modified non-linear mixing function is proposed for WAKE-ROFB which makes it better suited to hardware implementation. The high degree of parallelism allows efficient implementation on processors having instruction-level parallelism, and leads naturally to high-speed pipelined hardware implementations. The recommended variant runs at 340 Mbps on a 266 MHz Pentium II and 270 Mbps on a 100 MHz TriMedia VLIW CPU, while a 2000 gate hardware implementation of the same cipher achieves 200 Mbps from a 50 MHz clock. A higher speed variant achieves 600 Mbps, 340 Mbps and 400 Mbps respectively with some loss of security, while needing slightly less hardware.

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