Abstract
The requirements for a processor, in terms of its characteristics such as RISC (Reduced Instruction Set Computer), CISC (Complex Instruction Set Computer), bitwidth, instruction set, and for the communication and memory bandwidth differ for each application to be implemented. Furthermore, the required characteristic can be different at runtime, because the application has to react to the demands of the environment. Image processing is a good example for this scenario, because this application domain needs to adapt, depending on the content of the camera frames. Integrated, e.g., in a robot, the time variant requirements for the image processing applications are obvious. Sometimes gestures, obstacles, moving targets, etc. need to be detected within a high-resolution picture obtained by one or more cameras. For such applications, a novel Runtime Adaptive Multi-Processor System-on-Chip (RAMPSoC) was invented to provide an adaptive hardware architecture at design- and at runtime. This way, new degrees of freedom in system design and runtime support are provided. To program such a flexible multiprocessor system, an efficient design methodology is of high importance to hide the complexity of the underlying hardware. In addition, a runtime operating system is needed to handle the resource management and the runtime scheduling of the applications. In this chapter, the hardware architecture, the design methodology, and the runtime operating system of RAMPSoC are described. Furthermore, a brief overview about reconfigurable computing and dynamic and partial reconfiguration are given.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Similar content being viewed by others
Notes
- 1.
“Xilinx MicroBlaze Reference Guide”; Available at http://www.xilinx.com.
- 2.
“Xilkernel v3_00_a”; EDK 9.1i, December 12, 2006. Available at http://www.xilinx.com.
References
J. Becker, R. Hartenstein, Configware and Morphware going Mainstream; Elsevier Journal of Systems Architecture JSA (Special Issue on Reconfigurable Systems), October 2003
M. Berekovic, A. Kanstein, B. Mei, Mapping MPEG Video Decoders on the ADRES Reconfigurable Array Processor for Next Generation Multi-Mode Mobile Terminals; In Proc. of Global Signal Processing Conferences & Expos for the Industry: TV to Mobile (GSPX 2006), Amsterdam, Netherlands, March 29–30, 2006
P. Bertin, D. Roncin, J. Vuillemin, Introduction to Programmable Active Memories; Systolic Array Processor, Prentice Hall, pp. 300–309, 1989
C. Bobda, T. Haller, F. Mühlbauer, D. Rech, S. Jung, Design of Adaptive Multiprocessor on Chip Systems; In Proc. of the 20th Annual Conference on Integrated Circuits and Systems Design (SBCCI 2007), Copacabana, Rio de Janeiro, pp. 177–183, Sept. 3–6, 2007
L. Braun, D. Göhringer, T. Perschke, V. Schatz, M. Hübner, J. Becker, Adaptive real time image processing exploiting two dimensional reconfigurable architecture; Journal of Real-Time Image Processing, Springer, vol. 4, no. 2, pp.109–125, 2009
D. Burke, J. Wawrzynek, K. Asanovic, A. Krasnov, A. Schultz, G. Gibeling, P.-Y. Droz, RAMP Blue: Implementation of a Manycore 1008 Processor System; In Proc of RSSI 2008, July 2008
A. Cappelli, A. Lodi, C. Mucci, M. Toma, F. Campi, A Dataflow Control Unit for C-to-Configurable Pipelines Compilation Flow; In Proc. of IEEE 12th Int’l. Symposium on Field-Programmable Customs Computing Machines (FCCM 2004), Napa Valley, CA, USA, pp. 332–333, April 20–23, 2004
C. Chang, J. Wawrzynek, R. W. Broderson, BEE2: A High-End Reconfigurable Computing System; IEEE Design and Test of Computers, vol. 22, no. 2, pp. 114–125, 2005
C. Claus, W. Stechele, A. Herkersdorf, Autovision - A Run-time Reconfigurable MPSoC Architecture for future Driver Assistance Systems; Information Technology Journal, vol. 49, no. 3, pp. 181–187, June 20, 2007
K. Compton, S. Hauck, Reconfigurable Computing: A Survey of Systems and Software; ACM Computing Surveys, vol. 23, no. 2, pp. 171–210, 2002
G. Estrin, Organization of Computer Systems-The Fixed Plus Variable Sructure Computer; In Proc. of Western Joint Computer Conference, pp. 33–40, 1960
D. Göhringer, J. Becker, High Performance Reconfigurable Multi-Processor-Based Computing on FPGAs; In Proc. of the 24th IEEE International Parallel and Distributed Processing Symposium (IPDPS 2010), Atlanta, USA, April, 2010
D. Göhringer, M. Hübner, M. Benz, J. Becker, A Design Methodology for Application Partitioning and Architecture Development of Reconfigurable Multiprocessor Systems-on-Chip; In Proc. of the 18th Annual International IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2010), Charlotte, USA, May, 2010
D. Göhringer, M. Hübner, L. Hugot-Derville, J. Becker, Message Passing Interface Support for the Runtime Adaptive Multi-Processor System-on-Chip RAMPSoC; In Proc. of the 10th International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS X), Samos, Greece, July 2010
D. Göhringer, M. Hübner, E. Nguepi Zeutebouo, J. Becker, CAP-OS: Operating System for Runtime Scheduling, Task Mapping and Resource Management on Reconfigurable Multiprocessor Architectures; In Proc. of Reconfigurable Architectures Workshop (RAW 2010), Atlanta, USA, April, 2010
D. Göhringer, B. Liu, M. Hübner, J. Becker, Star-Wheels Network-on-Chip featuring a self-adaptive mixed topology and a synergy of a circuit- and a packet-switching communication protocol; In Proc. of the International Conference on Field Programmable Logic and Applications (FPL2009), Praha, Czech Republic, August/September, 2009
D. Göhringer, J. Luhmann, J. Becker, GenerateRCS: A High-Level Design Tool for Generating Reconfigurable Computing Systems, In Proc. of the IEEE International Conference on Very Large Scale Integration (VLSI-SoC 2009), Florianopolis, Brazil, October, 2009
R. Hartenstein, A Decade of Reconfigurable Computing: A Visionary Retrospective; In Proc. of Design, Automation and Test in Europe (DATE 2001), Munich, Germany, pp.642–649, March 12–16, 2001
R. Hartenstein, Why We Need Reconfigurable Computing Education; RC-Education Workshop, Karlsruhe, Germany, 2006
S. Hauck, A. DeHon, Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation; Morgan Kaufmann Series in Systems on Silicon, 2007
J. Howard, S. Dighe, Y. Hoskote et al., A 48-Core IA-32 Message-Passing Processor with DVFS in 45nm CMOS; In Proc. of IEEE International Solid-State Circuits Conference (ISSCC 2010), San Francisco, CA, USA, Feb. 2010
P. Lysaght, B. Blodget, J. Mason, J. Young, B. Bridgford, Invited paper: Enhanced Architectures, Design Methodologies and CAD Tools for Dynamic Reconfiguration of Xilinx FPGAs; In Proc. of the International Conference on Field Programmable Logic and Applications (FPL 2006), Madrid, Spain, pp. 1–6, August 2006
nVIDIA® Tesla™, GPU Computing Technical Brief, Version 1.0.0, May 2007
K. Paulsson, M. Hübner, H. Zou, J. Becker, Realization of Real-Time Control Flow Oriented Automotive Applications on a Soft-core Multiprocessor System based on Xilinx Virtex-II FPGAs; In Proc. of International Workshop on Applied Reconfigurable Computing (ARC 2005), Algarve, Portugal, pp. 103–110, Feb. 22–23, 2005
B. Radunovic, An Overview of Advances in Reconfigurable Computing Systems; In Proc. of the 32nd Hawaii International Conference on System Science, January 1999
N. Voros, A. Rosti, M. Hübner, Dynamic System Reconfiguration in Heterogeneous Platforms: The MORPHEUS Approach; Springer, Netherlands, 2009
A. Thomas, J. Becker, Dynamic Adaptive Routing Techniques In Multigrain Dynamic Reconfigurable Hardware Architectures; In Proc. of the International Conference on Field Programmable Logic and Applications (FPL 2004), Antwerp, August 2004
M. Ullmann, B. Grimm, M. Huebner, J. Becker, An FPGA Run-Time System for Dynamical On-Demand Reconfiguration; In Proc. of Reconfigurable Architectures Workshop (RAW 2004), Santa Fé, USA, 2004
W. Wolf, The Future of Multiprocessor Systems-on-Chips; In Proceedings of the Design Automation Conference (DAC 2004), San Diego, USA, pp. 681–685, June 7–11, 2004
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2011 Springer Science+Business Media, LLC
About this chapter
Cite this chapter
Göhringer, D., Hübner, M., Becker, J. (2011). Adaptive Multiprocessor System-on-Chip Architecture: New Degrees of Freedom in System Design and Runtime Support. In: Hübner, M., Becker, J. (eds) Multiprocessor System-on-Chip. Springer, New York, NY. https://doi.org/10.1007/978-1-4419-6460-1_6
Download citation
DOI: https://doi.org/10.1007/978-1-4419-6460-1_6
Published:
Publisher Name: Springer, New York, NY
Print ISBN: 978-1-4419-6459-5
Online ISBN: 978-1-4419-6460-1
eBook Packages: EngineeringEngineering (R0)