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NoC Modeling and Topology Exploration

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Designing 2D and 3D Network-on-Chip Architectures

Abstract

This chapter describes two of the most important tasks for designing NoC-based systems dealing with NoC modeling, as well as the topology exploration. For this purpose, state-of-the-art architectural solutions are discussed and open research topics are highlighted. Additionally, this chapter provides a description of alternative traffic models used as input to the NoC domain for evaluating the efficiency of various architectural parameters. The last topics discussed in this chapter are topology synthesis and application mapping onto the derived NoC architecture under various constraints.

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Authors and Affiliations

  1. Department of Computer Science and Engineering, School of Applied Sciences, Frederick University, Y. Frederickou Str., Pallouriotisa 7, Nicosia, 1036, Cyprus

    Konstantinos Tatas

  2. Department of Computer Science, School of Electrical and Computer Engineering, National Technical University of Athens, Heroon Polytechneiou, Zographou Campus 9, 157 80, Athens, Greece

    Kostas Siozios & Dimitrios Soudris

  3. Department of Electronic Systems, Royal Institute of Technology, ECS/ICT/KTH Forum 120, 164 40, Kista, Sweden

    Axel Jantsch

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  1. Konstantinos Tatas
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  2. Kostas Siozios
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  3. Dimitrios Soudris
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  4. Axel Jantsch
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Correspondence to Konstantinos Tatas .

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Tatas, K., Siozios, K., Soudris, D., Jantsch, A. (2014). NoC Modeling and Topology Exploration. In: Designing 2D and 3D Network-on-Chip Architectures. Springer, New York, NY. https://doi.org/10.1007/978-1-4614-4274-5_2

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  • DOI: https://doi.org/10.1007/978-1-4614-4274-5_2

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