Abstract
Network-on-chip implementations are typically complex in the design of the routers and the network interfaces. The resource consumption of such routers and network interfaces approaches the size of an in-order processor pipeline. For the job of just moving data between processors, this may be considered too much overhead. This paper presents a lightweight network-on-chip solution. We build on the S4NOC for the router design and add a minimal network interface. The presented architecture supports the transfer of single words between all processor cores. Furthermore, as we use time-division multiplexing of the router and link resources, the latency of such transfers is upper bounded. Therefore, this network-on-chip can be used for real-time systems. The router and network interface together consume around 6% of the resources of a RISC processor pipeline.
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Notes
- 1.
The original design is available in VHDL at https://github.com/t-crest/s4noc, while a rewrite in Chisel [2] has been made available at https://github.com/schoeberl/one-way-shared-memory.
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Acknowledgment
We would like to thank Constantina Ioannou for bringing up the idea of simply using a FIFO as a network interface.
The work presented in this paper was partially funded by the Danish Council for Independent Research | Technology and Production Sciences under the project PREDICT (http://predict.compute.dtu.dk/), contract no. 4184-00127A.
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Schoeberl, M., Pezzarossa, L., Sparsø, J. (2019). A Minimal Network Interface for a Simple Network-on-Chip. In: Schoeberl, M., Hochberger, C., Uhrig, S., Brehm, J., Pionteck, T. (eds) Architecture of Computing Systems – ARCS 2019. ARCS 2019. Lecture Notes in Computer Science(), vol 11479. Springer, Cham. https://doi.org/10.1007/978-3-030-18656-2_22
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