Abstract
In this paper, we implement and evaluate a self-partial reconfiguration (Self-PR) system, where configuration data for partial reconfiguration (PR) is stored in the hard macro memory on FPGA, and PR is performed from the inside of FPGA. As a result, in the case of the smallest PR region, the time required for Self-PR is about 2.8 ms, 97% less than using JTAG interface. The usage of hard macro memory blocks is about 21% of the total resources. We additionally implement and evaluate a mechanism that compresses the configuration data for PR, and the module that decompresses the data in the FPGA. As a result, the usage of hard macro memory blocks was reduced to 3% of the total resources. The increase in resource usage and the decrease in FMax due to addition of decompress circuit were quite limited, and there was no additional latency. Therefore, Self-PR with compressed configuration data can be performed in the same speed as when the compression mechanism was not utilized.
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Fukui, S., Kawamata, Y., Shibata, Y. (2020). A Self-partial Reconfiguration Framework with Configuration Data Compression for Intel FPGAs. In: Barolli, L., Hussain, F., Ikeda, M. (eds) Complex, Intelligent, and Software Intensive Systems. CISIS 2019. Advances in Intelligent Systems and Computing, vol 993. Springer, Cham. https://doi.org/10.1007/978-3-030-22354-0_39
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DOI: https://doi.org/10.1007/978-3-030-22354-0_39
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