Abstract
Random numbers are widely employed in cryptography and security applications, and they represent one of the main aspects to take care of along a security chain. They are employed for creation of encryption keys, and if generation process is weak, the whole chain can be compromised: weaknesses could be exploited to retrieve the key, thus breaking even the strongest cipher. This paper presents the architecture of a digital Random Number Generator (RNG) IP-core to be employed as hardware accelerator for cryptographically secure applications. Such design has been developed starting from specifications based on literature and standards, and in order to assess the randomness degree of generated output, it has been successfully validated through the official NIST Statistical Test Suite. Finally the RNG IP-core has been characterized on Field Programmable Gate Array (FPGA) and ASIC standard-cell technologies: on Intel Stratix IV FPGA it offers a throughput of 720 Mbps requiring up to 6000 Adaptive Logic Modules, while on 45 nm it reaches a throughput of 4 Gbps with a complexity of 119 kGE.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Similar content being viewed by others
Notes
- 1.
CTR is an abbreviation for Counter.
References
Barker E, Kelsey J (2016) Recommendation for Random Bit Generator (RBG) constructions. Special Publication 800-90C, NIST
Barker E, Kelsey J (2015) Recommendation for random number generation using deterministic random bit generators. Special Publication 800-90A, NIST
Lo Bello L, Mariani R, Mubeen S, Saponara S (2019) Recent advances and trends in on-board embedded and networked automotive systems. IEEE Trans Ind Inf 15:1038–1051
Pelzl J, Paar C (2011) Understanding cryptography. Springer, Berlin
Dang QH (2015) Secure hash standard. Technical report, NIST
Dichtl M, Golić JD (2007) High speed true random number generation with logic gates only. In: Cryptographic hardware and embedded systems—CHES 2007. Lecture Notes in Computer Science, vol 4727. Springer, Berlin, 45–62
Vasyltsov I, Hambardzumyan E, KimBohdan Y-S, Karpinskyy B (2008) Fast digital TRNG based on metastable ring oscillator. In: Cryptographic hardware and embedded systems—CHES 2008. Lecture Notes in Computer Science, vol 5154. Springer, Berlin, 164–180
Schmid M (2015) ECDSA—Application and implementation failures
Silvaco PDK 45nm Open Cell Library. https://www.silvaco.com/products/nangate/FreePDK45_Open_Cell_Library/index.html
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2020 Springer Nature Switzerland AG
About this paper
Cite this paper
Baldanzi, L., Crocetti, L., Falaschi, F., Belli, J., Fanucci, L., Saponara, S. (2020). Digital Random Number Generator Hardware Accelerator IP-Core for Security Applications. In: Saponara, S., De Gloria, A. (eds) Applications in Electronics Pervading Industry, Environment and Society. ApplePies 2019. Lecture Notes in Electrical Engineering, vol 627. Springer, Cham. https://doi.org/10.1007/978-3-030-37277-4_14
Download citation
DOI: https://doi.org/10.1007/978-3-030-37277-4_14
Published:
Publisher Name: Springer, Cham
Print ISBN: 978-3-030-37276-7
Online ISBN: 978-3-030-37277-4
eBook Packages: Physics and AstronomyPhysics and Astronomy (R0)