A Simple Analysis to Determine the Limits of a CMOS Technology to Implement SC DC-DC Converters

Abstract

This paper presents a simple analysis that allows to determine the maximum power density and efficiency of a SC DC-DC converter for a given CMOS technology. By determining the values of the ratio between the switches’ gate capacitance and channel width, and between the ON resistance and the channel width, together with the parasitic capacitances from the flying capacitors, it is possible to plot the efficiency as a function of the power density for a given input and output voltage of the converter, allowing to quickly determine both the expected efficiency and clock frequency ranges of the converter, for a given CMOS technology.

1 Introduction

Nowadays, with the growing number of Internet-of-things (IoT) devices, the collection of real live raw data from innumerous processes has greatly increased, e.g., in industrial, health, transportation, communications processes and others [1]. This raw data can be analyzed inside of the IoT device thus distributing the data processing capabilities and decreasing the reaction time. This sensing and processing of information costs energy. Hence, it is extremely important to have efficient systems, in a macro scale it contributes for reducing the carbon footprint, and at a small scale, it allows improving the battery life of devices thus reducing maintenance costs.

There are several energy sources, like solar, piezoelectrical, thermal, and others [2]. This energy can be fed directly to the system, and/or be stored in an energy storing device, like a battery or supercapacitor. These energy sources produce a variable voltage, which requires the use of a Power Management Unit (PMU) to obtain a constant output voltage. The PMU provides a bridge between the energy sources and the system using, for example, DC-DC converters. These can be inductive or capacitive, where the latter has receiving a lot of attention in recent years since they are composed by switches and capacitors that are native in CMOS technology and thus, they can be easily integrated, resulting in a smaller footprint and cost, and still achieve high performance values [2,3,4,5,6].

The Switched-Capacitor (SC) DC-DC converters transfer charge from the input to the output through a capacitor, where the frequency at which the charge is transferred will determine the output voltage value of the converter. This charge transferring is controlled by a clock signal, allowing for different circuit configurations on each clock phase. The quality of both the capacitors and switches will affect the converter’s energy efficiency and power per area value [6,7,8]. The characteristics of the passive devices depend on the CMOS technology node for the system implementation, for example, the lower the CMOS node, the higher the capacitance per area of the capacitors. This is because smaller oxide thickness means higher capacitance values. However, small oxide thickness also means lower breakdown voltage values and larger current leakage. The same goes for switches, the lower the node, the higher switching frequency can be. This raises the question, what is the expected performance for each technological node? To answer this, this work shows an analysis that characterizes both the capacitors and switches of the 130 nm bulk CMOS technology into a set of coefficients that are used to determine the converter efficiency and power per area. This can be applied to any technology node.

2 Relationship to Technological Innovation for Life Improvement

The IoT devices can enhance our life quality in many ways, e.g., increasing the surgery span of patient with medical embedded devices, like pacemakers, by increase the battery life of the devices. Such devices can also be used to monitoring our health, which can give us a better control of our daily life needs. There are several number of other examples in different areas, where all these devices, which need energy to operate, will benefit from energy efficient PMUs. The energy improvement of such devices will consequently have a direct impact on the human’s life quality.

3 SC DC-DC Converter Theoretical Analysis

Figure 1 shows the schematic of a Step-down Series-Parallel (SP) SC DC-DC converter with a Conversion Ratio (CR) of 1/2. It is composed by 1 flying capacitor $C_{FLY}$ and 4 switches, where $S_{1,3}$ are ON in the phase $\phi_{1}$ and $S_{2,4}$ are ON in phase $\phi_{2}$, where $\phi_{1,2}$ are two clock signals complementary to each other. Hence, on $\phi_{1}$, $C_{FLY}$ connects between the input voltage $V_{IN}$ and the output voltage ${\text{V}}_{\text{OUT}}$, and on $\phi_{2} ,$ $C_{FLY}$ connects between $V_{OUT}$ and ground. In the schematic it is also represented the $C_{FLY}$ parasitic capacitances by $\alpha$ and $\beta$, these refer to the top and bottom parasitic capacitance, respectively, as percentage of $C_{FLY}$. Assuming that $V_{OUT}$ is kept at a constant voltage, the charge equations can be drawn:

Fig. 1.

Simplified schematic of the SP 1/2 SC DC-DC converter in each clock phase [3, 4].

$$ \left( {V_{IN} - V_{OUT} } \right)\,C_{FLY} + V_{IN} \,\left( {\alpha\,C_{FLY} } \right) = V_{OUT} \,\left( {C_{FLY} +\alpha\,C_{FLY} } \right) +\Delta q_{o}^{{\upphi_{2} }} , $$

(1)

$$ - V_{OUT} \,C_{FLY} = \left( {V_{OUT} - V_{IN} } \right)\,C_{FLY} + V_{OUT} \,\left( {\beta\,C_{FLY} } \right) +\Delta q_{o}^{{\upphi_{1} }} , $$

(2)

$$ V_{OUT} \,\left( {C_{FLY} +\alpha\,C_{FLY} } \right) = \left( {V_{IN} - V_{OUT} } \right)\,C_{FLY} + V_{IN} \,\left( {\alpha\,C_{FLY} } \right) -\Delta q_{i}^{{\upphi_{1} }} \,. $$

(3)

where $\Delta q_{o}^{{\upphi_{1,2} }}$ are the amount of charge absorbed by $V_{OUT}$, in the respective phase, and $\Delta q_{i}^{{\upphi_{1} }}$ the amount of charge drawn by the circuit from $V_{IN}$, in this case only during $\phi_{1}$.

These equations can be solved in respect to $\Delta q_{i}^{{\upphi_{1} }}$, $\Delta q_{o}^{{\upphi_{1} }}$, and $\Delta q_{o}^{{\upphi_{2} }}$, and used to determine the input and output current and power:

$$ I_{IN} = \varDelta q_{i}^{{\phi_{1} }} \,F_{CLK} = C_{FLY} \,\left( {V_{IN} \,\left( {1 + \alpha } \right) - V_{OUT} \,\left( {2 + \alpha } \right)} \right) , $$

(4)

$$ I_{OUT} = \left( {\varDelta q_{o}^{{\phi_{1} }} + \varDelta q_{o}^{{\phi_{2} }} } \right)\,F_{CLK} = C_{FLY} \,F_{CLK} \,\left( {V_{IN} \,\left( {2 + \alpha } \right) - V_{OUT} \,\left( {4 + \alpha + \beta } \right)} \right) , $$

(5)

$$ P_{IN} = V_{IN} \,I_{IN} = C_{FLY} \,F_{CLK} \,V_{IN} \,\left( {V_{IN} \,\left( {1 + \alpha } \right) - V_{OUT} \,\left( {2 + \alpha } \right)} \right) , $$

(6)

$$ P_{OUT} = V_{OUT} \,I_{OUT} = C_{FLY} \,F_{CLK} \,V_{OUT} \,\left( {V_{IN} \,\left( {2 + \alpha } \right) - V_{OUT} \,\left( {4 + \alpha + \beta } \right)} \right) . $$

(7)

The converter efficiency $\eta$ can be obtained by (8) and its output impedance $R_{OUT}$ by (9). Both $V_{OUT}$ and $F_{CLK}$ can be determined by (10) and (11), where $R_{L}$ is the load resistor and $P_{OUT} = V_{OUT}^{2} /R_{L}$.

$$ \eta = \frac{{P_{OUT} }}{{P_{IN} }} = \frac{{V_{OUT} \,\left( {V_{IN} \,\left( {2 + \alpha } \right) - V_{OUT} \,\left( {4 + \alpha + \beta } \right)} \right)}}{{V_{IN} \,\left( {V_{IN} \,\left( {1 + \alpha } \right) - V_{OUT} \,\left( {2 + \alpha } \right)} \right)}} , $$

(8)

$$ R_{OUT} = \frac{{CR\,V_{IN} - V_{OUT} }}{{I_{OUT} }} = \frac{{V_{IN} - 2\,V_{OUT} }}{{2\,C_{FLY} \,F_{CLK} \,\left( {V_{in} \,\left( {2 + \alpha } \right) - V_{OUT} \,\left( {4 + \alpha + \beta } \right)} \right)}}\left. = \right|_{\alpha ,\beta = 0} \;\frac{1}{{4\,C_{FLY} \,F_{CLK} }} , $$

(9)

$$ V_{OUT} = I_{OUT} R_{L} \Rightarrow V_{OUT} = \frac{{C_{FLY} \,F_{CLK} \,R_{L} \,V_{IN} \,\left( {2 + \alpha } \right)}}{{1 + C_{FLY} \,F_{CLK} \,R_{L} \,\left( {4 + \alpha + \beta } \right)}} , $$

(10)

$$ F_{CLK} = \frac{{V_{OUT} }}{{C_{FLY} \,R_{L} \,\left( {V_{IN} \,\left( {2 + \alpha } \right) - V_{OUT} \,\left( {4 + \alpha + \beta } \right)} \right)}} = \frac{{P_{OUT} }}{{C_{FLY} \,V_{OUT} \,\left( {V_{IN} \,\left( {2 + \alpha } \right) - V_{OUT} \,\left( {4 + \alpha + \beta } \right)} \right)}} . $$

(11)

Figure 2 shows the converter’s $\eta$ and $F_{CLK}$ as a function of $V_{IN}$ for different values of $\alpha$ and $\beta$, with $C_{FLY} = 100$ pF, and $P_{out} = 1$ mW. The graphs show that while both parasitic capacitances have a negative impact on both $\eta$ and $F_{CLK}$, the top parasitic capacitance has a smaller impact when compared to the bottom parasitic capacitance. Moreover, it pushes the peak efficiency for lower $V_{IN}$ values while decreasing $F_{CLK}$ for the same input/output ratio. This is because the charge absorbed on $\phi_{1}$ is supplied to $V_{OUT}$ on $\phi_{2}$. This acts like a parallel 1/1 converter and thus allowing the converter to work at a lower $F_{CLK}$ value for the same input/output voltage ratio. Hence, in this topology, when implementing the $C_{FLY}$ the highest parasitic plate should be connected as the top parasitic capacitance [9]. These equations were validated through electrical simulations in [10, 11].

Fig. 2.

Efficiency as a function of ${V}_{{{IN}}}$, for ${V}_{{{OUT}}}$ = 0.9 V, ${C}_{{{FLY}}}$ = 100 pF, and ${P}_{{{out}}}$ = 1 mW.

Expression (8) assumes that the clock phases are long enough to allow $C_{FLY}$ to completely charge (or discharge), however, the finite $R_{ON}$ value of the switches cause partial charging depending on $F_{CLK}$, hence it will have an impact on the converter efficiency [5]. According to [5], $R_{OUT}$ can be re-written to take in the effect of partial charging:

$$ R_{OUT} = \frac{1}{\gamma }\,\frac{1}{{4\,C_{FLY} \,F_{CLK} }} , $$

(12)

this equation is identical to (9) except for a scaling factor, $\gamma$, which accounts for incomplete charging [5]. Let $\tau^{\prime}$ be everything else that is in the exponential before $F_{CLK}$ $(\tau^{\prime} = 2\,R_{{ON_{tot} }} \,C_{FLY} )$, then the number of time constant in a period sets the value of $\gamma$. For 3 $\tau^{\prime}$, the $\gamma$ value is 90.05%, for 4 $\tau^{\prime}$, it is 96.40%, and for 5 $\tau^{\prime}$ it is 98.66%. Thus, for values lower than $4\tau^{\prime}$, the value of $\gamma$ drops significantly. Hence, $4\tau^{\prime}$ offers a good compromise point for sizing the converter switches without having a significant impact on the converter’s efficiency. The $4\tau^{\prime}$ allows to size the switches $R_{ON}$ and thus determining the transistor’s $W$. This allows to determine the power required to charge the gate switches’ parasitic capacitance $(C_{GG} )$, which will also impact the converter’s efficiency.

Figure 3 shows the converter’s schematic with its ON switches replaced by the respective $R_{ON}$. Both $\phi_{1}$ and $\phi_{2}$ have the same time constant given by:

Fig. 3.

Simplified schematic of the converter with the switches replaced by $R_{ON}$.

$$ \tau = R_{{ON_{tot} }} C_{FLY} = \frac{1}{{2F_{CLK} }} , $$

(13)

where $R_{{ON_{tot} }} = R_{{ON_{S1} }} + R_{{ON_{S2} }}$ is the total resistance value of switches in series per phase. Assuming that $R_{{ON_{S1} }} = R_{{ON_{S2} }} = R_{{O{\text{N}}}}$ which means that $R_{ON} = R_{{ON_{tot} }} /2$, then, the $R_{ON}$ value for the $4\tau^{\prime}$ operation point is given by

$$ R_{{ON_{total} }} = \frac{1}{{4\tau^{\prime}}} = \frac{1}{{8\,C_{FLY} \,F_{CLK} }} \Rightarrow R_{ON} = \frac{1}{{16\,C_{FLY} \,F_{CLK} }} . $$

(14)

For small drain-to-source voltages $(V_{DS} \ll V_{GS} - V_{TH} )$, the switch $R_{ON}$ and $C_{GG}$ are given by:

$$ R_{ON} \cong \frac{L}{{C_{ox}\upmu_{n} W\left( {V_{GS} - V_{TH} } \right)}} \approx \frac{{k_{R} }}{W} , $$

(15)

$$ C_{GG} = C_{GD} + C_{GS} \cong WLC_{ox} + WC_{ov} \approx k_{C} W . $$

(16)

These equations show that $R_{ON}$ is inversely proportional to the transistor’s width $(W)$, and that $C_{GG}$ is directly proportional to $W$. Furthermore, if $V_{GS}$, $L$, $C_{ox}$ and $\mu_{n}$ are kept constant, and $V_{DS} \ll V_{GS} - V_{TH}$, then the previous equations can be approximated by a constant coefficient, $k_{R}$ and $k_{C}$, that relates both $R_{ON}$ and $C_{GG}$ with $W$ [10, 12]. Hence, $C_{GG}$ can be given by (17). The switches’ power dissipation can be determined by summing all the switches’ $C_{GG}$ and multiplying it by $F_{CLK}$ and the switches drive voltage $V_{SW}$ squared, as shown in Eq. (19). Notice that $P_{SW}$ is given by the sum of the $k_{R}$ and $k_{C}$ coefficients of each switch, where N is the total number of switches, where $K_{SW} = k_{{C_{1} }} \,k_{{R_{1} }} + k_{{C_{2} }} \,k_{{R_{2} }} + \ldots + k_{{C_{N} }} \,k_{{R_{N} }}$.

$$ C_{GG} = \frac{{K_{R} \,K_{C} }}{{R_{ON} }} = 16\,k_{C} \,k_{R} \,C_{FLY} \,F_{CLK} , $$

(17)

$$ P_{SW} = \left( {C_{{GG_{S1} }} + C_{{GG_{S2} }} + C_{{GG_{S3} }} + C_{{GG_{S4} }} } \right)\,F_{CLK} \,V_{SW}^{2} = $$

(18)

$$ = 16\,\left( {k_{{C_{1} }} \,k_{{R_{1} }} + \ldots + k_{{C_{N} }} \,k_{{R_{N} }} } \right)\,C_{FLY} \,F_{CLK}^{2} \,V_{SW}^{2} = 16\,K_{SW} \,C_{FLY} \,F_{CLK}^{2} \,V_{SW}^{2} . $$

(19)

The effect of $P_{SW}$ can now be added to the converter’s efficiency, resulting in

$$ \eta = \frac{{P_{OUT} }}{{P_{IN} + P_{SW} }} = \frac{{V_{OUT} \,\left( {V_{IN} \,\left( {\alpha + 2} \right) - V_{OUT} \,\left( {\alpha + \beta + 4} \right)} \right)}}{{16\,F_{CLK} \,V_{OUT}^{2} \,K_{SW} + V_{IN}^{2} \,\left( {\alpha + 1} \right) - V_{IN} \,V_{OUT} \,\left( {\alpha + 2} \right)}}. $$

(20)

Due to the $F_{CLK}^{2}$ in (19), $F_{CLK}$ does not cancel out in (20). Thus, replacing $F_{CLK}$ by (11) and considering that $C_{FLY}$ can be given by the capacitance area $A_{c}$ times $C_{den}$ of the device chosen to implement it, e.g. $10\,{\text{fF}}/\upmu{\text{m}}^{2}$ in the MOS capacitor. Then, $C_{FLY}$ can be re-written by $C_{FLY} = A_{c} \times C_{den}$. This gives $\eta$ as a function of $P_{OUT}$ per capacitance area, i.e. power density, as shown below.

$$ \eta = \frac{{V_{OUT} \,\left( {V_{IN} \,\left( {\alpha + 2} \right) - V_{OUT} \,\left( {\alpha +\beta + 4} \right)} \right)}}{{V_{IN}^{2} \,\left( {\alpha + 1} \right) - V_{IN} \,V_{OUT} \,\left( {\alpha + 2} \right) + \frac{{16\,K_{SW} \,P_{OUT} \,V_{OUT} }}{{A_{c} \,C_{den} \,\left( {V_{IN} \,\left( {2 +\alpha} \right) - V_{OUT} \,\left( {4 +\alpha +\beta} \right)} \right)}}}}. $$

(21)

The equation above allows to determine the converter’s efficiency as a function of the power density for a given $V_{IN}$ and $V_{OUT}$, and for a given $K_{SW}$, which depends on the type of transistors chosen to implement the switches. Considering four different cases, where the transistors are all implemented by 1.2 V ($k_{R} = 577.40\,\Omega \cdot\upmu{\text{m}}^{2}$ and $k_{C} = 1.34\, {\text{fF}}/\upmu{\text{m}}^{2}$) and 3.3 V ($k_{R} = 5337.56 \,\Omega \cdot\upmu{\text{m}}^{2}$ and $k_{C} = 1.77\, {\text{fF}}/\upmu{\text{m}}^{2}$) NMOS transistors, 1.2 V ($k_{R} = 2709.51 \,\Omega \cdot\upmu{\text{m}}^{2}$ and $k_{C} = 1.41\, {\text{fF}}/\upmu{\text{m}}^{2}$) and 3.3 V ($k_{R} = 20570.40\,\Omega \cdot\upmu{\text{m}}^{2}$ and $k_{C} = 1.95 \,{\text{fF}}/\upmu{\text{m}}^{2}$) PMOS transistors, the $k_{R}$ and $k_{C}$ were taken for a $V_{GS} = 0.9$ V through electrical simulations. Figure 4 (a) and (b) show the efficiency (21) as a function of the power density for $V_{SW} = V_{OUT} = 0.9$ V and for $C_{FLY}$ implemented by a PMOS transistor ($C_{den} = 10 {\text{fF}}/\upmu{\text{m}}^{2}$, $\alpha = 4.5$ %, and $\beta \approx 0$ %). As expected, the graph clearly show that 1.2 V transistors are preferable in comparison with 3.3 V transistors. Furthermore, 1.2 V NMOS transistors allow maximizing the efficiency and power density. However, 1.2 V transistors may not be an option if their voltages exceed the transistor’s breakdown voltage. Moreover, 1.2 V NMOS requires $V_{GS} > V_{th}$, which in the case switch $S_{1}$ it would require a gate voltage higher than $V_{IN}$. Hence, choosing to implement $S_{1}$ with a 1.2 V PMOS transistor can be a good compromise given the complexity of the NMOS driver would require.

Fig. 4.

Converter’s ${\eta}$ as a function of ${P}_{{{OUT}}} /{A}_{{c}}$ for different switches’ implementation with ${V}_{{{OUT}}}$ = 0.9 V.

Figure 5 (a) and (b) show the efficiency (21) as a function of the power density with $S_{1,2,3}$ implemented with PMOS transistors and $S_{4}$ with an NMOS transistor, $C_{FLY}$ implemented with a PMOS transistor, and for $V_{OUT} = 0.9$ V. The graphs show that depending on the input voltage limit, the maximum power density, whilst keeping efficiency constant, is within the 10 to $100\,{\text{mW}}/{\text{mm}}^{2}$, depending if either 1.2 V or 3.3 V transistors are used.

Fig. 5.

Converter’s ${\eta}$ as a function of ${P}_{{{OUT}}} /{A}_{{c}}$ with ${S}_{1,2,3}$ implemented with PMOS transistor and ${S}_{4}$ with NMOS transistor, for ${V}_{{{OUT}}}$ = 0.9 V.

It is important to notice that once the switch is sized, the switches’ $R_{ON}$ is fixed throughout the whole $V_{IN}$ range. In the previous graphs, the switch’s $R_{ON}$ was modified according to the $V_{IN}$ value. In a real scenario, the converter’s minimum $V_{IN}$ value must be fixed, which sets the minimum $R_{ON}$ value. Hence, the previous analysis is used to set $R_{{ON_{Min} }}$ and then $\eta$ is recalculated using the constant $R_{{ON_{Min} }}$ value throughout the whole $V_{IN}$ range.

Figure 6 (a) and (b) show $\eta$ recalculated using the $R_{ON}$ calculated for different $V_{IN}$, for $10\,{\text{mW}}/{\text{mm}}^{2}$ and $100\,{\text{mW}}/{\text{mm}}^{2}$. The efficiency values after $V_{{IN_{limit} }}$ are not drawn because $F_{CLK}$ increases beyond the $4\tau^{\prime}$ limit resulting in incomplete settling, making the equation no longer valid. These graphs show that as $V_{{IN_{limit} }}$ gets closer to the voltage CR there is a significantly impact on $\eta$, especially at high power density values, such as $100\,{\text{mW}}/{\text{mm}}^{2}$. Hence, avoiding working close to the CR voltage value (1.8) is recommend because the value of $R_{ON}$ is extremely low. Furthermore, the frequency increases rapidly close to the CR voltage value, hence any deviation from that point would cause $V_{OUT}$ to rapidly deviate from the 0.9 V target. Nonetheless, the previous analysis with the variable $R_{ON}$ and with fixed $R_{ON}$ are quite similar when working under the maximum power density $( < 100\,{\text{mW}}/{\text{mm}}^{2} )$ and far enough from the CR voltage value $(V_{IN} > 1.85)$. The efficiency plot should be analyzed together with $F_{CLK}$ because, as Fig. 6 (b) shows, to achieve a power density of $100\,{\text{mW}}/{\text{mm}}^{2}$ the converter must work at frequencies of 10 to 100 MHz, which adds complexity to the system design, mainly the clock generator and the switch drivers. Hence lower power densities, such has the ones in Fig. 6 (a) may be preferable, due to the lower $F_{CLK}$ value.

Fig. 6.

Converter’s ${\eta}$ with both the ${C}_{{{FLY}}}$ and the switches’ parasitic capacitances for a fixed ${R}_{{{ON}}}$ value determined by the minimum ${V}_{{{IN}}}$ value of the converter, for ${V}_{{{OUT}}}$ = 0.9 V.

4 Conclusions

This paper describes a theorical analysis that allows characterizing the performance of an SC DC-DC converter for a given technological node. In this case, the 130 nm CMOS technology was chosen to implement a 1/2 SP SC DC-DC converter for converting an input voltage range of 2.3 to 1.8 V to an output voltage of 0.9 V. The results show that with this topology and technology the maximum efficiency would be around 80% and the power density per area in the range of 10 to 100 mW/mm², depending on the transistors chosen to implement the passive devices.