Location via proxy:   [ UP ]  
[Report a bug]   [Manage cookies]                
Skip to main content
Springer Nature Link
Log in

PMC-Based Dynamic Adaptive CPU and DRAM Power Modeling

  • Conference paper
  • First Online:
Algorithms and Architectures for Parallel Processing (ICA3PP 2020)

Part of the book series: Lecture Notes in Computer Science ((LNTCS,volume 12452))

Abstract

The problem of high power consumption has become one of the main obstacles that affect the reliability, stability, and performance of high-performance computers. How to get the power of CPU and memory instantaneously and accurately is an important basis for evaluating their power’s optimization methods. At present, much work has been done to model CPU and memory power using the performance monitoring counter (PMC). Most of these models are static, which fit and estimate the power of the corresponding CPU or memory by collecting and counting key performance monitoring events. However, when the performance behavior of the application changes dramatically with time, the accuracy of the real-time power measurement values will decline, because the performance monitoring values used in the power model can not fit the power values well in a long time. In order to solve this problem, we first analyze the changing features of application performance indicators when CPU or memory power changes, especially the correlation between PMC events and CPU and memory power, and then propose a dynamic adaptive power modeling method (DAPM) based on PMC events using dynamic adaptive technology, which is used for real-time power measurement of CPU and memory. The DAPM can realize the adaptive selection/matching of the model by introducing the power measurement data at the node level, and enhance the real-time power measurement accuracy by dynamically expanding the model library. Besides, the running cost of the DAPM is low. Compared with other PMC power models, DAPM can achieve lower CPU and DRAM power error rates. The error rates of three conventional PMC power models are Isci’s model 7%(CPU), Singh’s 7.2%(CPU), and Bircher’s 6.7%(CPU) and 8.8%(DRAM), while the CPU error rate of DAPM is less than 2%, and the DRAM error rate is less than 5.5%.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Log in via an institution

Subscribe and save

Springer+ Basic
$34.99 /Month
  • Get 10 units per month
  • Download Article/Chapter or eBook
  • 1 Unit = 1 Article or 1 Chapter
  • Cancel anytime
Subscribe now

Buy Now

Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 84.99
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 109.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Similar content being viewed by others

References

  1. AMD: BIOS and Kernel Developer’s Guide (BKDG) for AMD Family 14h Models 00h–0Fh Processors, January 2011

    Google Scholar 

  2. Basmadjian, R., Ali, N., Niedermeier, F., de Meer, H., Giuliani, G.: A methodology to predict the power consumption of servers in data centres. In: Proceedings of the 2nd International Conference. e-Energy 2011. ACM, New York, May 2011

    Google Scholar 

  3. Bellosa, F.: The benefits of event—driven energy accounting in power-sensitive systems. In: Proceedings of the 9th Workshop on ACM SIGOPS European Workshop (2000)

    Google Scholar 

  4. Bircher, W.L., John, L.: Complete system power estimation using processor performance events. IEEE Trans. Comput. 61(4), 563–577 (2010)

    Article  MathSciNet  Google Scholar 

  5. Chou, C., Bhuyan, L.N., Wong, D.: \(\mu \)dpm: dynamic power management for the microsecond era. In: 2019 IEEE International Symposium on High Performance Computer Architecture (HPCA), pp. 120–132 (2019)

    Google Scholar 

  6. Economou, D., Rivoire, S., Kozyrakis, C., Ranganathan, P.: Full-system power analysis and modeling for server environments. In: Proceedings of the Workshop on Modeling, Benchmarking, and Simulation, pp. 70–77 (2006)

    Google Scholar 

  7. Fan, X., Weber, W.D., Barroso, L.A.: Power provisioning for a warehouse-sized computer (2007)

    Google Scholar 

  8. Feihao, W., et al.: A holistic energy-efficient approach for a processor-memory system. Tsinghua Sci. Technol. 24(4), 468–483 (2019)

    Google Scholar 

  9. Gholkar, N., Mueller, F., Rountree, B., Marathe, A.: PShifter: Feedback-based dynamic power shifting within HPC jobs for performance. In: Proceedings of the 27th International Symposium on High-Performance Parallel and Distributed Computing. New York, NY, USA (2018)

    Google Scholar 

  10. Hanson, H., et al.: Processor-memory power shifting for multi-core systems (2012)

    Google Scholar 

  11. Heath, T., Diniz, B., Horizonte, B., Carrera, E.V., Bianchini, R.: Energy conservation in heterogeneous server clusters. In: Proceedings of the 10th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP 2005), pp. 186–195. ACM (2005)

    Google Scholar 

  12. Henning, J.L.: SPEC CPU2006 benchmark descriptions. ACM SIGARCH Comput. Archit. News 34(4), 1–17 (2006)

    Article  Google Scholar 

  13. Wang, H., et al.: Distributed systems meet economics: pricing in the cloud. In: Proceedings of the 2nd USENIX Conference on Hot Topics in Cloud Computing (2010)

    Google Scholar 

  14. Intel: Intel 82599 10 GbE Controller Datasheet, November 2019

    Google Scholar 

  15. Intel: Intel xeon processor e5–2660 v3 (2020). https://ark.intel.com/content/www/us/en/ark/products/81706/intel-xeon-processor-e5-2660-v3-25m-cache-2-60-ghz.html

  16. Isci, C.: Runtime power monitoring in high-end processors: methodology and empirical data. In: Proceedings of International Symposium on Microarchitecture (2003)

    Google Scholar 

  17. Juan, C., et al.: Analyzing time-dimension communication characterizations for representative scientific applications on supercomputer systems. Front. Comput. Sci. 13(6), 1228–1242 (2019)

    Google Scholar 

  18. Khatamifard, S.K., Wang, L., Das, A., Kose, S., Karpuzcu, U.R.: Powert channels: a novel class of covert communication exploiting power management vulnerabilities. In: 2019 IEEE International Symposium on High Performance Computer Architecture (HPCA), pp. 291–303 (2019)

    Google Scholar 

  19. Khavari Tavana, M., Sun, Y., Bohm Agostini, N., Kaeli, D.: Exploiting adaptive data compression to improve performance and energy-efficiency of compute workloads in multi-GPU systems. In: 2019 IEEE International Parallel and Distributed Processing Symposium (IPDPS), pp. 664–674 (2019)

    Google Scholar 

  20. Lee, B.C., Brooks, D.M.: Accurate and efficient regression modeling for microarchitectural performance and power prediction. ACM SIGOPS Oper. Syst. Rev. 40(5), 185

    Google Scholar 

  21. Lefurgy, C., Wang, X., Ware, M.: Power capping: a prelude to power shifting. Cluster Comput. 11, 183–195 (2008)

    Article  Google Scholar 

  22. Lewis, A., Ghosh, S., Tzeng, N.F.: Run-time energy consumption estimation based on workload in server systems. In: Workshop on Power Aware Computing and Systems, HotPower 2008, 7 December 2008, San Diego, CA, USA, Proceedings (2008)

    Google Scholar 

  23. Luszczek, P.R., Bailey, D.H., Dongarra, J.J., Kepner, J., Takahashi, D.: S12-the HPC challenge (HPCC) benchmark suite. In: Proceedings of the ACM/IEEE SC2006 Conference on High Performance Networking and Computing, 11–17 November 2006, Tampa, FL, USA (2006)

    Google Scholar 

  24. Patel, T., Tiwari, D.: Perq: fair and efficient power management of power-constrained large-scale computing systems. In: Proceedings of the 28th International Symposium on High-Performance Parallel and Distributed Computing. New York, NY, USA (2019)

    Google Scholar 

  25. Powell, M.D., Biswas, A., Emer, J.S., Mukherjee, S.S., Yardi, S.M.: CAMP: a technique to estimate per-structure power at run-time using a few simple parameters. In: 15th International Conference on High-Performance Computer Architecture (HPCA), 14–18 February 2009, Raleigh, North Carolina, USA (2009)

    Google Scholar 

  26. Qian, S., et al.: Adjusting matching algorithm to adapt to dynamic subscriptions in content-based publish/subscribe systems. In: 2018 IEEE International Conference on Parallel Distributed Processing with Applications (2018)

    Google Scholar 

  27. Basmadjian, R., de Meer, H.: Evaluating and modeling power consumption of multi-core processors. In: Proceedings of the 2012 3rd International Conference on Future Energy Systems: Where Energy, Computing and Communication Meet (2012)

    Google Scholar 

  28. Raghavendra, R., Ranganathan, P., Talwar, V., Wang, Z., Zhu, X.: No “power” struggles: coordinated multi-level power management for the data center. In: Proceedings of the 13th International Conference on Architectural Support for Programming Languages and Operating Systems. New York, NY, USA (2008)

    Google Scholar 

  29. Rivoire, S., Ranganathan, P., Kozyrakis, C.: A comparison of high-level full-system power models. In: Workshop on Power Aware Computing and Systems, HotPower 2008, 7 December 2008, San Diego, CA, USA, Proceedings (2008)

    Google Scholar 

  30. Singh, K., Bhadauria, M., McKee, S.A.: Real time power estimation and thread scheduling via performance counters. ACM SIGARCH Comput. Archit. News 37(2), 46 (2009)

    Article  Google Scholar 

  31. Song, S., Su, Chunyi, C., Kirk, W.: A simplified and accurate model of power-performance efficiency on;emergent GPU architectures, pp. 673–686 (2013)

    Google Scholar 

  32. Tang, G., Jiang, W., Xu, Z., Liu, F., Wu, K.: Zero-cost, fine-grained power monitoring of datacenters using non-intrusive power disaggregation (2015)

    Google Scholar 

  33. Tiwari, A., Laurenzano, M.A., Carrington, L., Snavely, A.: Modeling power and energy usage of HPC kernels. In: IEEE International Parallel and Distributed Processing Symposium Workshops and Phd Forum (2012)

    Google Scholar 

  34. Wang, H., Cao, Y.: Predicting power consumption of GPUs with fuzzy wavelet neural networks. Parallel Comput. 44, 18–36

    Google Scholar 

  35. Widyawan, Z.M.I., Nugroho, L.E.: Adaptive motion detection algorithm using frame differences and dynamic template matching method. In: Ubiquitous Robots and Ambient Intelligence, International Conference (2012)

    Google Scholar 

  36. Wikipedia: Least squares (2020). en.wikipedia.org/wiki/Leastsquares

  37. Wikipedia: Pearson correlation coefficient (2020). http://en.wikipedia.org/wiki/Pearson_correlation_coefficient

  38. Wikipedia: Perf wiki (2020). perf.wiki.kernel.org/index.php/MainPage

  39. Yong, D., Juan, C., Yuhua, T., Junjie, W., Huiquan, W., Enqiang, Z.: Lazy scheduling based disk energy optimization method. Tsinghua Sci. Technol. 25(2), 203–216 (2020)

    Google Scholar 

  40. Yoshii, K., Iskra, K., Gupta, R., Beckman, P., Coghlan, S.: Evaluating power-monitoring capabilities on IBM Blue Gene/P And Blue Gene/Q. In: 2012 IEEE International Conference on Cluster Computing (CLUSTER) (2012)

    Google Scholar 

  41. Zhang, J., Huo, H., Fang, Q., Zhang, D.: System and method for managing baseboard management controller (2008)

    Google Scholar 

Download references

Acknowledgements

This work is supported in part by the Advanced Research Project of China under grant number 31511010203 and the Research Program of NUDT grant number ZK18-03-10.

Author information

Authors and Affiliations

  1. National University of Defense Technology, Changsha, Hunan, China

    Yunfang Zhang, Yong Dong, Juan Chen, Zhixin Ou & Yuan Yuan

Authors
  1. Yunfang Zhang
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Yong Dong
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Juan Chen
    View author publications

    You can also search for this author in PubMed Google Scholar

  4. Zhixin Ou
    View author publications

    You can also search for this author in PubMed Google Scholar

  5. Yuan Yuan
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Yunfang Zhang .

Editor information

Editors and Affiliations

  1. Columbia University, New York, NY, USA

    Meikang Qiu

Rights and permissions

Reprints and permissions

Copyright information

© 2020 Springer Nature Switzerland AG

About this paper

Check for updates. Verify currency and authenticity via CrossMark

Cite this paper

Zhang, Y., Dong, Y., Chen, J., Ou, Z., Yuan, Y. (2020). PMC-Based Dynamic Adaptive CPU and DRAM Power Modeling. In: Qiu, M. (eds) Algorithms and Architectures for Parallel Processing. ICA3PP 2020. Lecture Notes in Computer Science(), vol 12452. Springer, Cham. https://doi.org/10.1007/978-3-030-60245-1_7

Download citation

Publish with us

Policies and ethics

Search

Navigation