Abstract
Design space exploration can be used to find a power-efficient architectural design for a given application, such as the best suited configuration of a heterogeneous system from soft cores of different types, given area and throughput constraints. We show how to integrate design space exploration into a static scheduling algorithm for a streaming task graph application with parallelizable tasks and solve the resulting combined optimization problem by an integer linear program (ILP). We demonstrate the improvements by our strategy with ARM big and LITTLE soft cores and synthetic task graphs.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Similar content being viewed by others
Notes
- 1.
In [10], we used parallel efficiency, i.e. speedup over core count, and separated the difference in performance between core types from the speedup by using an additional variable \(r_{i,j}\).
- 2.
We did not express the maximum width explicitly in Sect. 2 but included it in the definition of speedup.
- 3.
Please remember that also during task execution, power is composed from “idle” power and power on top, so that idle power mostly indicates static power.
- 4.
A smaller step than the area \(A_{LITTLE}\) of the smaller core would not change anything.
References
Lal Shimpi, A.: Samsung Details Exynos 5 Octa Architecture & Power at ISSCC 2013 (2013). https://www.anandtech.com/show/6768/. Accessed 01 Mar 2021
Duhem, F., Muller, F., Aubry, W., Le. Gal, B., Négru, D., Lorenzini, P.: Design space exploration for partially reconfigurable architectures in real-time systems. J. Syst. Architect. 59(8), 571–581 (2013). https://doi.org/10.1016/j.sysarc.2013.06.007
Eindhoven Technical University, Electronic Systems: Dataflow Benchmark Suite (DFbench) (2010). http://www.es.ele.tue.nl/dfbench/
Hautala, I.: From dataflow models to energy efficient application specific processors. Ph.D. thesis, Oulu University, Finland (2019)
Holmbacka, S., Keller, J.: Workload type-aware scheduling on big.LITTLE platforms. In: Ibrahim, S., Choo, K.-K.R., Yan, Z., Pedrycz, W. (eds.) ICA3PP 2017. LNCS, vol. 10393, pp. 3–17. Springer, Cham (2017). https://doi.org/10.1007/978-3-319-65482-9_1
Holzer, M., Knerr, B., Rupp, M.: Design space exploration for real-time reconfigurable computing. In: Proceedings of the 41st Asilomar Conference on Signals, Systems and Computers, pp. 1981–1985 (2007). https://doi.org/10.1109/ACSSC.2007.4487583
Kahn, G.: The semantics of a simple language for parallel programming. In: Proceedings of the IFIP Congress on Information Processing, pp. 471–475. North-Holland (1974)
Kessler, C.W., Melot, N., Eitschberger, P., Keller, J.: Crown scheduling: energy-efficient resource allocation, mapping and discrete frequency scaling for collections of malleable streaming tasks. In: 23rd International Workshop on Power and Timing Modeling, Optimization and Simulation, pp. 215–222 (2013)
Li, Z., et al.: Using design space exploration for finding schedules with guaranteed reaction times of synchronous programs on multi-core architecture. J. Syst. Architect. 74, 30–45 (2017). https://doi.org/10.1016/j.sysarc.2016.12.003
Litzinger, S., Keller, J., Kessler, C.: Scheduling moldable parallel streaming tasks on heterogeneous platforms with frequency scaling. In: Proceedings of the 27th European Signal Processing Conference (EUSIPCO 2019), September 2019
Litzinger, S., Keller, J.: Code generation for energy-efficient execution of dynamic streaming task graphs on parallel and heterogeneous platforms. Concurrency and Computation: Practice and Experience n/a(n/a), e6072 (2021). https://doi.org/10.1002/cpe.6072
Maestre, R., Kurdahi, F., Fernandez, M., Hermida, R., Bagherzadeh, N., Singh, H.: Kernel scheduling techniques for efficient solution space exploration in reconfigurable computing. J. Syst. Architect. 47(3), 277–292 (2001). https://doi.org/10.1016/S1383-7621(00)00050-3
Melot, N., Kessler, C., Keller, J.: Improving energy-efficiency of static schedules by core consolidation and switching off unused cores. In: Proceedings of the International Conference on Parallel Computing (ParCo 2015), pp. 285–294. IOS Press (2016). https://doi.org/10.3233/978-1-61499-621-7-285
Melot, N., Kessler, C., Keller, J., Eitschberger, P.: Fast Crown scheduling heuristics for energy-efficient mapping and scaling of moldable streaming tasks on manycore systems. ACM Trans. Archit. Code Optim. 11(4) (2015)
Melot, N., Kessler, C., Keller, J., Eitschberger, P.: Co-optimizing core allocation, mapping and dvfs in streaming programs with moldable tasks for energy efficient execution on manycore architectures. In: Proceedings of the 19th International Conference on Application of Concurrency to System Design (ACSD-2019), Aachen, Germany. IEEE, June 2019. https://doi.org/10.1109/ACSD.2019.00011
Oppermann, J., Sittel, P., Kumm, M., Reuter-Oppermann, M., Koch, A., Sinnen, O.: Design-space exploration with multi-objective resource-aware modulo scheduling. In: Yahyapour, R. (ed.) Euro-Par 2019. LNCS, vol. 11725, pp. 170–183. Springer, Cham (2019). https://doi.org/10.1007/978-3-030-29400-7_13
Sarma, S., Dutt, N.: Cross-layer exploration of heterogeneous multicore processor configurations. In: Proc. 28th International Conference on VLSI Design and 14th International Conference on Embedded Systems. IEEE (2015). https://doi.org/10.1109/VLSID.2015.3
Torggler, M., Keller, J., Kessler, C.W.: Asymmetric crown scheduling. In: Kotenko, I.V., Cotronis, Y., Daneshtalab, M. (eds.) 25th Euromicro International Conference on Parallel, Distributed and Network-based Processing, PDP 2017, St. Petersburg, Russia, March 6–8, 2017. pp. 421–425. IEEE Computer Society (2017). https://doi.org/10.1109/PDP.2017.22
Uscumlic, B., Enrici, A., Pacalet, R., Gharbi, A., Apvrille, L., Natarianni, L., Roullet, L.: Design space exploration with deterministic latency guarantees for crossbar mpsoc architectures. In: Proc. IEEE International Conference on Communications (ICC). pp. 1–7 (2020). https://doi.org/10.1109/ICC40277.2020.9149076
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2021 Springer Nature Switzerland AG
About this paper
Cite this paper
Keller, J., Litzinger, S., Kessler, C. (2021). Combining Design Space Exploration with Task Scheduling of Moldable Streaming Tasks on Reconfigurable Platforms. In: Derrien, S., Hannig, F., Diniz, P.C., Chillet, D. (eds) Applied Reconfigurable Computing. Architectures, Tools, and Applications. ARC 2021. Lecture Notes in Computer Science(), vol 12700. Springer, Cham. https://doi.org/10.1007/978-3-030-79025-7_7
Download citation
DOI: https://doi.org/10.1007/978-3-030-79025-7_7
Published:
Publisher Name: Springer, Cham
Print ISBN: 978-3-030-79024-0
Online ISBN: 978-3-030-79025-7
eBook Packages: Computer ScienceComputer Science (R0)