Abstract
Application-Specific Instruction-set Processors (ASIP) are ideal for realizing physical layer signal processing algorithms in communication systems as they offer performance similar to hard-wired datapath implementations, while providing sufficient programmability to adapt with the continuously evolving communication standards. Several design choices needs to be made while developing an algorithm for a specific signal processing function, such as the selection of the algorithm itself, choice of the mathematical operations and numerical precision, that affects the throughput, area and power consumption of ASIP implementation. Traditionally, the algorithm development and the ASIP architecture exploration is performed as separate processes resulting in large design time or a sub-optimal solution. This paper presents a simple methodology for the algorithm-ASIP designer(s) to understand the impact of various algorithmic design choices on the ASIP performance and make the right design choices at very early stage, thereby reducing the design time at least by a factor of 2.8x in algorithm research and development.
Supported by Flanders Innovation and Entrepreneurship (VLAIO).
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References
Cadence Design Systems Inc.: Tensilica customizable processors (2019). https://ip.cadence.com/ipportfolio/tensilica-ip/xtensa-customizable
Codasip Ltd.: Codasip Studio (2019). https://www.codasip.com/custom-processor/
Eusse, J., Williams, C., Leupers, R.: CoEx: a novel profiling-based algorithm/architecture co-exploration for ASIP design. In: 2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), pp. 1–8 (2013). https://doi.org/10.1109/ReCoSoC.2013.6581520
Eusse, J., et al.: Pre-architectural performance estimation for ASIP design based on abstract processor models. In: 2014 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV), pp. 133–140 (2014). https://doi.org/10.1109/SAMOS.2014.6893204
Hoare, R.R., et al.: Rapid VLIW processor customization for signal processing applications using combinational hardware functions. EURASIP J. Adv. Signal Process. 2006(1), 1–23 (2006). https://doi.org/10.1155/ASP/2006/46472
Ienne, P., Leupers, R.: Customizable Embedded Processors: Design Technologies and Applications. Morgan Kaufmann Publishers Inc., San Francisco (2007)
Jordans, R., Diken, E., Jozwiak, L., Corporaal, H.: BuildMaster: efficient ASIP architecture exploration through compilation and simulation result caching. In: 17th International Symposium on Design and Diagnostics of Electronic Circuits Systems, pp. 83–88 (2014). https://doi.org/10.1109/DDECS.2014.6868768
Jordans, R., Jóźwiak, L., Corporaal, H.: Instruction-set architecture exploration of VLIW ASIPs using a genetic algorithm. In: 2014 3rd Mediterranean Conference on Embedded Computing (MECO), pp. 32–35 (2014). https://doi.org/10.1109/MECO.2014.6862720
Jozwiak, L., et al.: ASAM: automatic architecture synthesis and application mapping. Microprocess. Microsyst. 37(8 PARTC), 1002–1019 (2013). https://doi.org/10.1016/j.micpro.2013.08.006
Kato, T., et al.: A CDFG generating method from C program for LSI design. In: 2008 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2008, pp. 936–939 (2008). https://doi.org/10.1109/APCCAS.2008.4746177
Lapinskii, V.S., Jacome, M.F., De Veciana, G.A.: Application-specific clustered VLIW datapaths: early exploration on a parameterized design space. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(8), 889–903 (2002). https://doi.org/10.1109/TCAD.2002.800451
Meloni, P., Pomata, S., Tuveri, G., Secchi, S., Raffo, L., Lindwer, M.: Enabling fast ASIP design space exploration: an FPGA-based runtime reconfigurable prototyper. VLSI Des. 2012, 11:11 (2012). https://doi.org/10.1155/2012/580584
Pomata, S., et al.: Exploiting binary translation for fast ASIP design space exploration on FPGAs. In: 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 566–569 (2012). https://doi.org/10.1109/DATE.2012.6176533
Rosien, M., Smit, G., Krol, T.: Generating a CDFG from C/C++ code, pp. 200–202. STW Technology Foundation (2002). Imported from DIES
Synopsys Inc.: Synopsys IP designer (2019). https://www.synopsys.com/dw/ipdir.php?ds=asip-designer
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Gomony, M.D., Jivanescu, M., Olaziregi, N. (2023). Towards ASIP Architecture-Driven Algorithm Development. In: Wehrmeister, M.A., Kreutz, M., Götz, M., Henkler, S., Pimentel, A.D., Rettberg, A. (eds) Analysis, Estimations, and Applications of Embedded Systems. IESS 2019. IFIP Advances in Information and Communication Technology, vol 576. Springer, Cham. https://doi.org/10.1007/978-3-031-26500-6_8
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