Abstract
The integration of potentially untrustworthy intellectual property (IP) blocks into a System-on-Chip (SoC) poses significant risks, including data exfiltration and corruption due to unauthorized writes to memory or peripheral devices. Conventional countermeasures, such as memory protection or management units, tend to provide coarse protection granularity and impose substantial hardware overhead for embedded devices.
In this paper, we introduce \(\mathrm {DD\text {-}MPU}\), a custom memory protection unit specifically designed for individual third-party IPs. Our proposed solution features low area overhead and fine protection granularity while automatically adapting to dynamic system states by actively monitoring bus transfers and switching between different protection rules.
In our evaluation, we demonstrate the efficacy of the \(\mathrm {DD\text {-}MPU}\) by integrating it into an SoC to isolate a potentially malicious accelerator block from the rest of the system. The area overhead of our approach for a single instance in a 22 nm technology ASIC node is a mere 0.3%.
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Acknowledgements
This research was funded by the German Federal Ministry for Education and Research (BMBF) in project 16ME0233.
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Heinz, C., Koch, A. (2023). \(\mathrm {DD\text {-}MPU}\): Dynamic and Distributed Memory Protection Unit for Embedded System-on-Chips. In: Silvano, C., Pilato, C., Reichenbach, M. (eds) Embedded Computer Systems: Architectures, Modeling, and Simulation. SAMOS 2023. Lecture Notes in Computer Science, vol 14385. Springer, Cham. https://doi.org/10.1007/978-3-031-46077-7_19
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DOI: https://doi.org/10.1007/978-3-031-46077-7_19
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