Abstract
The vast majority of the existing studies on GC-eDRAM focus on implementation in mature technology nodes (most often 0.18 μm CMOS and no lower than 65 nm CMOS) and at nominal supply voltages. This chapter studies the suitability of GC-eDRAM beyond these design spaces by analyzing aggressive technology scaling, down to 28 nm CMOS, and aggressive supply voltage scaling, all the way to the subthreshold (sub-V T) domain. First, the analytical retention time model developed in Chap. 3 is validated for a scaled 28 nm CMOS node. Second, a conventional 2T GC topology is optimized for sub-V T operation. Simulations show successful sub-V T operation for a 2T GC-eDRAM array in 0.18 μm CMOS. Furthermore, a 2T GC-eDRAM array implemented in a scaled 40 nm CMOS can be operated successfully down to the near-V T domain, while simultaneous aggressive technology and voltage scaling to the sub-V T domain are not recommended.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Notes
- 1.
Note that in the sub-V T region, these mechanisms are still negligible, as compared to sub-V T conduction. However, as shown in Sect. 6.3.3.2, at near-V T supplies, some of the mechanisms still must be considered.
- 2.
The LVT devices were left out of the figure for display purposes, as their leakage is significantly higher than the leakage of other devices.
- 3.
Some of the leakage components are not modeled for the I/O devices; however, this does not impact our analysis, as the PMOS HVT already provides the lowest total leakage.
- 4.
This is verified for the chosen implementation at the minimum feasible bias in Sect. 6.5.
References
Calhoun B, Chandrakasan A (2007) A 256-kb 65-nm sub-threshold SRAM design for ultra-low-voltage operation. IEEE J Solid-State Circuits 42(3):680–688
Calhoun BH, Wang A, Chandrakasan A (2005) Modeling and sizing for minimum energy operation in subthreshold circuits. IEEE J Solid-State Circuits 40(9):1778–1786
Chiu YW, Lin JY, Tu MH, Jou SJ, Chuang CT (2011) 8T single-ended sub-threshold SRAM with cross-point data-aware write operation. In: Proceedings of IEEE/ACM international symposium on low-power electronics and design (ISLPED), pp 169–174
Chun KC, Jain P, Lee JH, Kim C (2011) A 3T gain cell embedded DRAM utilizing preferential boosting for high density and low power on-die caches. IEEE J Solid-State Circuits 46(6):1495–1505
Constantin J, Dogan A, Andersson O, Meinerzhagen P, Rodrigues J, Atienza D, Burg A (2012) TamaRISC-CS: An ultra-low-power application-specific processor for compressed sensing. In: Proceedings of IEEE/IFIP international conference on VLSI system-on-chip (VLSI-SoC), pp 159–164
Hanson S, Seok M, Lin YS, Foo Z, Kim D, Lee Y, Liu N, Sylvester D, Blaauw D (2009) A low-voltage processor for sensing applications with picowatt standby mode. IEEE J Solid-State Circuits 44(4):1145–1155
Lee Y, Chen MT, Park J, Sylvester D, Blaauw D (2010) A 5.42nW/kB retention power logic-compatible embedded DRAM with 2T dual-VT gain cell for low power sensing applications. In: Proceedings of IEEE Asian solid state circuits conference (A-SSCC), pp 1–4
Meinerzhagen PA, Andiç O, Treichler J, Burg AP (2011) Design and failure analysis of logic-compatible multilevel gain-cell-based DRAM for fault-tolerant VLSI systems. In: Proceedings of IEEE/ACM great lakes symposium on VLSI (GLSVLSI), pp 343–346
Meinerzhagen P, Andersson O, Mohammadi B, Sherazi Y, Burg A, Rodrigues J (2012) A 500 fW/bit 14 fJ/bit-access 4 kb standard-cell based sub-VT memory in 65nm CMOS. In: Proceedings of IEEE European solid-state circuits conference (ESSCIRC), pp 321–324
Meinerzhagen P, Teman A, Mordakhay A, Burg A, Fish A (2012) A sub-VT 2T gain-cell memory for biomedical applications. In: Proceedings of IEEE subthreshold microelectronics conference (SubVT), pp 1–3. doi:10.1109/SubVT.2012.6404318
Sinangil M, Verma N, Chandrakasan A (2008) A reconfigurable 65nm SRAM achieving voltage scalability from 0.25–1.2V and performance scalability from 20kHz–200MHz. In: Proceedings of IEEE European solid-state circuits conference (ESSCIRC), pp 282–285
Sinangil M, Verma N, Chandrakasan A (2009) A reconfigurable 8T ultra-dynamic voltage scalable (U-DVS) SRAM in 65 nm CMOS. IEEE J Solid-State Circuits 44(11):3163–3173
Teman A, Pergament L, Cohen O, Fish A (2011) A 250 mV 8 kb 40 nm ultra-low power 9T supply feedback SRAM (SF-SRAM). IEEE J Solid-State Circuits 46(11):2713–2726
Teman A, Pergament L, Cohen O, Fish A (2011) A minimum leakage quasi-static RAM bitcell. J Low Power Electron Appl 1(1):204–218
Teman A, Meinerzhagen P, Burg A, Fish A (2012) Review and classification of gain cell eDRAM implementations. In: Proceedings of IEEE convention of electrical and electronics engineers in Israel (IEEEI), pp 1–5
Teman A, Mordakhay A, Mezhibovsky J, Fish A (2012) A 40-nm sub-threshold 5T SRAM bit cell with improved read and write stability. IEEE Trans Circuits Syst II: Express Briefs 59(12):873–877
Teman A, Mordakhay A, Fish A (2013) Functionality and stability analysis of a 400 mV quasi-static RAM (QSRAM) bitcell. ELSEVIER Microelectron J 44(3):236–247
Author information
Authors and Affiliations
Rights and permissions
Copyright information
© 2018 Springer International Publishing AG
About this chapter
Cite this chapter
Meinerzhagen, P., Teman, A., Giterman, R., Edri, N., Burg, A., Fish, A. (2018). Aggressive Technology and Voltage Scaling (Down to the Subthreshold Domain). In: Gain-Cell Embedded DRAMs for Low-Power VLSI Systems-on-Chip. Springer, Cham. https://doi.org/10.1007/978-3-319-60402-2_6
Download citation
DOI: https://doi.org/10.1007/978-3-319-60402-2_6
Published:
Publisher Name: Springer, Cham
Print ISBN: 978-3-319-60401-5
Online ISBN: 978-3-319-60402-2
eBook Packages: EngineeringEngineering (R0)