Abstract
Power consumption becomes an important issue for modern processors. The off-chip buses consume considerable amount of total power [9,7]. One effective way to reduce power is to reduce the overall bus switching activities since they are proportional to the power. Up till now, the most effective technique in reducing the switching activities on the data buses is Frequent Value Encoding (FVE) that exploits abundant frequent value locality on the off-chip data buses. In this paper, we propose a technique that exploits more value locality that was overlooked by the FVE. We found that a significant amount of non-frequent values, not captured by the FVE, share common high-ordered bits. Therefore, we propose to extend the current FVE scheme to take bit-wise frequent values into consideration. On average, our technique reduces 48% switching activity. The average energy saving we achieved is 44.8%, which is 8% better than the FVE.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
Similar content being viewed by others
References
Basu, K., Choudhary, Q., Pisharath, J., Kandemir, M.: Power Protocol: Reducing Power dissipation on off-chip Data Buses. In: The 35th IEEE/ACM International symposium on Microarchitecture, pp. 345–355 (2002)
Benini, L., Macii, A., Macii, E., Poncino, M., Scarsi, R.: Synthesis of Low-Overhead Interfaces for Power-Efficient Communication Over Wide Buses. In: ACM/IEEE Design Automation Conference, pp. 128–133 (1999)
Cadence Corporation: http://www.cadence.com
Burger, D., Austin, T.: The SimpleScalar Tool Set, Version 2.0., Technical Report 1342, Universoty of Wisconsin-Madison, Computer science Department (1997)
Messmer, H.: The Indispensable PC Hardware Book, 4th edn. Addison-Wesley, Reading (2002)
The Mosis Service: http://www.mosis.com/
Stan, M.R., Burleson, W.P.: Bus-invert coding for low-power I/O. IEEE Transactions on very Large Scale Integration (VLSI) systems 3, 49–58 (1995)
Yang, J., Gupta, R.: FV Encoding for Low-Power Data I/O. In: ACM/IEEE International Symposium on Low Power Electronic Design, pp. 84–87 (2001)
Zhang, Y., Yang, J., Gupta, R.: Frequent Value Locality and Value-centric Data Cache Design. In: The Ninth International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS IX), pp. 150–159 (2000)
Efthymiou, A., Garside, J.D.: An Adaptive Serial-Parallel CAM Architecture for Low-Power Cache Blocks. In: Proceedings of the International Symposium On Low Power Electronics and Design (2002)
Citron, D., Rudolph, L.: Creating a wider bus using caching techniques. In: Proceedings of the first International symposium on High Performance Computer Architecture, January 1995, pp. 90–99 (1995)
Farrens, M., Park, A.: Dynamic base register caching: A technique for reducing address bus width. In: Proceedings of 18th Annual International Symposium on Computer Architecture, Toronto, Canada, May 1991, pp. 128–137 (1991)
Musoll, E., Lang, T., Cortadella, J.: Working-zone encoding for reducing the energy in microprocessor address buses. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 6 (1998)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2003 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Suresh, D.C., Yang, J., Zhang, C., Agrawal, B., Najjar, W. (2003). FV-MSB: A Scheme for Reducing Transition Activity on Data Buses. In: Pinkston, T.M., Prasanna, V.K. (eds) High Performance Computing - HiPC 2003. HiPC 2003. Lecture Notes in Computer Science, vol 2913. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-24596-4_6
Download citation
DOI: https://doi.org/10.1007/978-3-540-24596-4_6
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-20626-2
Online ISBN: 978-3-540-24596-4
eBook Packages: Springer Book Archive