Abstract
A method for testability-oriented optimization of sequential circuits implemented using FPGAs with embedded memory is presented. It specifies the content of those memory words which are not defined by the conventional FSM synthesis. The experimental results confirm its effectiveness; for the largest examined circuit, the self-test session required to achieve an acceptable level of fault escapes for the optimized design, obtained using the proposed procedure, is almost 106 times shorter than for the non-optimized design. The proposed method does not involve any extra circuitry or speed degradation. Also, it does not require any extra reconfiguration during self-testing.
This work was supported by the State Committee for Scientific Research of Poland under grant no. 4 T11D 014 24
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Krasniewski, A. (2004). Optimization of Testability of Sequential Circuits Implemented in FPGAs with Embedded Memory. In: Becker, J., Platzner, M., Vernalde, S. (eds) Field Programmable Logic and Application. FPL 2004. Lecture Notes in Computer Science, vol 3203. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-30117-2_128
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