Abstract
This paper proposes a new adaptable FPGA logic element based on fracturable 6-LUTs, which fundamentally alters the longstanding belief that a 4-LUT is the most efficient area/delay tradeoff. We will describe theory and benchmarking results showing a 15% performance increase with 12% area decrease vs. a standard BLE4. The ALM structure is one of a number of architectural improvements giving Altera’s 90nm Stratix II architecture a 50% performance advantage over its 130nm Stratix predecessor.
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Hutton, M. et al. (2004). Improving FPGA Performance and Area Using an Adaptive Logic Module. In: Becker, J., Platzner, M., Vernalde, S. (eds) Field Programmable Logic and Application. FPL 2004. Lecture Notes in Computer Science, vol 3203. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-30117-2_16
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DOI: https://doi.org/10.1007/978-3-540-30117-2_16
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