Abstract
There are many similarities between modern 3D graphics chips and FPGAs: a shader based graphic chip can be viewed as a highly domain specific and very coarse-grained reconfigurable logic device. Our goal is to see how a finegrained FPGA can be used to implement the pixel and vertex shader stages of a graphics pipeline, and how well the two methods compare in terms of speed, power, flexibility, and usability, initially by implementing Direct-X 9 pixel shader programs using Xilinx Virtex-II FPGAs.
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© 2004 Springer-Verlag Berlin Heidelberg
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Thomas, D.B., Luk, W. (2004). Implementing Graphics Shaders Using FPGAs. In: Becker, J., Platzner, M., Vernalde, S. (eds) Field Programmable Logic and Application. FPL 2004. Lecture Notes in Computer Science, vol 3203. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-30117-2_163
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DOI: https://doi.org/10.1007/978-3-540-30117-2_163
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-22989-6
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