Abstract
In this paper we highlight the suitability of MDSP architecture to exploit the data, algorithmic, and pipeline parallelism offered by video processing algorithms like the MPEG-2 for real-time performance. Most existing implementations extract either data or pipeline parallelism along with Instruction Level Parallelism (ILP) in their implementations. We discuss the design of MP@ML decoding system on shared memory MDSP platform and give insights on building larger systems like HDTV. We also highlight how the processor scalability is exploited. Software implementation of video decompression algorithms provides flexibility, but at the cost of being CPU intensive. Hardware implementations have a large development cycle and current VLIW dsp architectures are less flexible. MDSP platform offered us the flexibilty to design a system which could scale from four MSPs (Media Stream Processor is a logical cluster of one RISC and two DSP processors) to eight MSPs and build a single-chip solution including the IO interfaces for video/audio output. The system has been tested on CRA2003 board. Specific contributions include the multiple VLD algorithm and other heuristic approaches like early-termination IDCT for fast video decoding.
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References
International Standard ISO/IEC 11172-2 Information Technology: Coding of Moving Pictures and associated audio for the storage media at 1.5 Mbps
International Standard ISO/IEC 13818-2 Information Technology - Generic Coding of moving pictures and associated audio. Information: Video
Haskell, B., Puri, A., Netravali, A.: Digital Video: Introduction to MPEG2
Bhaskaran, V., Konstantinides, K.: Image and Video Compression Standards Algorithms and Architectures. Kulwer Academic Publicatons, Boston
Onoye, T., Masaki, T., Morimoto, Y., et al.: Single chip implementation of MPEG-2 decoder for HDTV level pictures. IEICE Trans. Fundamentals (March 1996)
Bala, A., Shah, D., Feng, W.-c., Panda, D.K.: Experiences with Software MPEG-2 Video Decompression on an SMP PC
Venkateswar, V.: Precision Requirements for IDCT Implementations on 340I. Tech. Report, Semiconductor & Process Design Center, Texas Instruments (February 1992)
Guttag, K., Gove, R.J., Van Aken, J.R.: A Single-Chip Multiprocessor for Multimedia: The MVP. IEEE Computer Graphics & Applications (November 1992)
Chen, W.H., Smith, C.H., Fralick, S.C.: A Fast Computational Algorithm for the DCT. IEEE Trans. on Communications COM-25 (1977)
Liao, H., Wolfe, A.: Available Parallelism in Video Applications. In: International Symposium on Microarchitecture (1997)
Tekalp, M.: Digital Video Processing. Prentice Hall PTR, Englewood Cliffs (1995)
Fujitsu: MPEG2 Decoder with embedded SDRAM, RAMPEG MB87P2030
Bilas, A., Fritts, J., Singh, J.P.: Real-time parallel MPEG-2 decoding in software. Princeton University Technical Report TR-516-96
Lee, W., Goldston, J., et al.: Real-time MPEG video codec on single chip multiprocessor. In: Proc. of the SPIE, Digital Video Compression on Personal Computers: Algorithms and Technologies, February 1994, vol. 2187, pp. 32–42 (1994)
Jeschke, H., Gaedke, K., Pirsch, P.: Multiprocessor Performance for Real-Time Processing of Video Coding Applications. IEEE Trans. on Circuits and Systems for Video Technology 2, 221–230 (1992)
Akiyama, T., Aono, H., Aoki, K., et al.: MPEG-2 Video Codec using Image Compression DSP. IEEE Trans. on Consumer Electronics 40, 466–472 (1994)
Ishiwata, S., Yamakage, T., et al.: A Single-Chip MPEG-2 Codec Based on Customizable Media Microprocessor. In: IEEE CICC 2002 (2002)
Sriram, S., Hung, C.-Y.: MPEG-2 video decoding on the TMS320C6X DSP architecture. In: IEEE Asilomar Conf. on Signals, Systems and Computers (1998)
Cradle Technologies, CRA2003 & CT3400 Hardware Architecture reference
Lee, R.B., et al.: Real-time software MPEG video decoder on multimedia-enhanced PA 7100LC processor. Hewlett-Packard Journal (April 1995)
Ishii, D., et al.: Parallel variable length decoding with inverse quantization for software MPEG-2 decoders. In: Proc. of 1997 workshop on SiPS (1997)
Intel: Using MMX instructions in a fast IDCT algorithm for MPEG decoding, Intel Application Note AP-528
Intel: Using MMX instructions to implement optimized motion compensation for MPEG1 video playback, Intel Application Note AP-529
Fogg, C.: Survey of software and hardware VLC architectures. In: SPIE. Image and Video Compression, vol. 2186 (1994)
Zhou, C.-G., Kohn, L., Rice, D., Kabir, I., Jabibi, A., Hu, X-P.: MPEG video decoding with UltraSPARC visual instruction set, Compcon (Spring 1995)
Huang, C.-Y., Landman, P.: A compact IDCT design for MPEG video decoding. In: Proc. 1997 IEEE workshop on Signal Processing Systems (SiPS) (November 1997)
IEEE standard specification for the implementation of 8 by 8 IDCT, IEEE standard 1180-1190
Verderber, M., Zemva, A., Lampret, D.: Hw/sw partitioned optimization and VLSI FPGA implementation of the MPEG-2 video decoder, SIGDA (2003)
Lei, S.-M., Sun, M.-T.: An entropy coding system for digital HDTV applications. IEEE transactions on circuits and systems for video technology 1, 147–155 (1991)
Philips, TriMedia TM-1300 Media Processor Data Book (September 2000)
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Yadav, G., Singh, R.K., Chaudhary, V. (2004). On Implementation of MPEG-2 Like Real-Time Parallel Media Applications on MDSP SoC Cradle Architecture. In: Yang, L.T., Guo, M., Gao, G.R., Jha, N.K. (eds) Embedded and Ubiquitous Computing. EUC 2004. Lecture Notes in Computer Science, vol 3207. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-30121-9_27
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DOI: https://doi.org/10.1007/978-3-540-30121-9_27
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