Abstract
This paper presents the design and evaluation of a cache coherence adapter for the cache-coherent non-uniform memory access multiprocessor system in which symmetric multiprocessor (SMP) nodes are interconnected via Xcent-Net. The SMP node is a 4-way symmetric multiprocessor subsystem based on the Intel Xeon processors, and Xcent-Net is a dual, adaptive-routed, virtual cut-through multistage interconnection network composed of hierarchical crossbar routers. The cache coherence adapter contains a directory and a remote access cache to support the directory-based cache coherence protocol customized for the SMP nodes on Xcent-Net. For any cache design, cache size and cache line size are crucial design parameters in terms of performance and implementation, and thus they are extensively evaluated. According to the simulation results, it is shown that a 128-Mbyte remote access cache with 64-byte lines is the best choice, where the average data access latency is 9.4 μs and the effective bandwidth is 6.8 Mbytes/s per node.
This study was supported in part by research funds from Chosun University, 2003.
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References
Hwang, K.: Advanced Computer Architecture: Parallelism, Scalability, Programmability, pp. 3–32. McGraq-Hill, Inc., New York (1993)
Protic, J., Tomasevic, M., Milutinovic, V.: An Overview of Distributed Shared Memory. In: Protic, J., Tomasevic, M., Milutinovic, V. (eds.) Distributed Shared Memory: Concepts and Systems, pp. 12–41. IEEE Computer Society Press, Los Alamitos (1998)
Lilja, D.J.: Cache Coherence in Large-Scale Shared-Memory Multiprocessors: Issues and Comparisons. ACM Computing Surveys 25, 303–338 (1993)
Tomasevic, M., Milutinovic, V.: Hardware Solutions for Cache Coherence in Shared- Memory Multiprocessor Systems. In: Tomasevic, M., Milutinovic, V. (eds.) The Cache Coherence Problem in Shared-Memory Multiprocessors: Hardware Solutions, pp. 57–67. IEEE Computer Society Press, Los Alamitos (1993)
Field, A.J., Harrison, P.G.: A Fixed-Point Model of a Distributed Consistency Protocol. In: Baccelli, F., Jean-Marie, A., Mitrani, I. (eds.) Quantitative Methods in Parallel Systems, Springer-Verlag, Distributed Shared Memory: Concepts and Systems, pp. 237–247. IEEE Computer Society Press, Los Alamitos (1995)
Agarwal, A., Simoni, R., Hennessy, J., Horowitz, M.: An Evaluation of Directory Schemes for Cache Coherence. In: Proc. 15th Int. Symp. on Computer Architecture, pp. 280–289 (1988)
Chaiken, D., Fields, C., Kurihara, K., Agarwal, A.: Directory-Based Cache Coherence in Large-Scale Multiprocessors. IEEE Computer 23, 49–58 (1990)
Intel Corporation: Intel Server Products (2003), http://developer.intel.com/design/servers/buildingblocks/
Lenoski, D., Laudon, J., Gharachorloo, K., Gupta, A., Hennessy, J.: The Directory-Based Cache Coherence Protocol for the DASH Multiprocessor. In: Proc. of 17th Int. Symp. on Computer Architecture, pp. 148–159 (1990)
Lenoski, D., Weber, W.-D.: Scalable Shared-Memory Multiprocessing, pp. 173–203. Morgan Kaufmann Publishers, San Francisco (1995)
Lovett, T., Clapp, R.: STiNG: A CC-NUMA Computer System for the Commercial Marketplace. In: Proc. of 23th Int. Symp. on Computer Architecture, pp. 308–317 (1996)
Laudon, J., Lenoski, D.: The SGI Origin: A ccNUMA Highly Scalable Server. In: Proc. of 24th Int. Symp. on Computer Architecture, pp. 241–251 (1997)
Park, K., Han, J.-S., Sim, W.-S., Hahn, W.-J.: Xcent-Net: A Hierarchical Crossbar Network for a Cluster-Based Parallel Architecture. In: Proc. of 8th Int. Conf. on Parallel and Distributed Computing and Systems, pp. 139–141 (1996)
Kim, T.G.: DEVSim++ User’s Manual. Ver. 1.0, Computer Engineering Research Lab., KAIST (1994)
Intel Corporation: The Intel Xeon Processor Family (2003), http://developer.intel.com/design/Xeon/
Heidelberger, P., Lavenberg, S.S.: Computer Performance Evaluation Methodology. IEEE Trans. on Computers 33, 1195–1220 (1984)
Allen, A.O.: Probability, Statistics, and Queueing Theory with Computer Science Applications, 2nd edn. Academic Press, London (1990)
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Moh, S., Shim, JH., Lee, YD., Lee, JA., Cho, BJ. (2003). Design and Evaluation of a Cache Coherence Adapter for the SMP Nodes Interconnected via Xcent-Net. In: Yazıcı, A., Şener, C. (eds) Computer and Information Sciences - ISCIS 2003. ISCIS 2003. Lecture Notes in Computer Science, vol 2869. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-39737-3_113
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DOI: https://doi.org/10.1007/978-3-540-39737-3_113
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