Abstract
A methodology for the power-efficient implementation of multimedia kernels based on reconfigurable hardware (FPGA) is introduced. The methodology combines various types of algorithmic transformations and high-level memory hierarchy exploration with register-transfer level design and implementation. An FPGA with an external memory was used for obtaining experimental results which prove the viability of the methodology. Comparisons among implementations with and without this optimization, prove that great power efficiency is achieved.
This work was partially supported by the project IST-34793-AMDREL which is funded by the E.C.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
Similar content being viewed by others
References
Compton, K., Hauck, S.: Reconfigurable Computing: A Survey of Systems and Software. ACM Computing Surveys 34(2), 171–210 (2002)
Catthoor, F., et al.: Data Acess and Storage Management or Embedded Programmable Processors. Kluwer Academic Publisher, Boston (2002)
Soudris, D., Zervas, N.D., Argyriou, A., Dasygenis, M., Tatas, K., Goutis, C., Thanailakis, A.: Data-Reuse and Parallel Embedded Architectures for Low-Power, Real-Time Multimedia Applications. In: Soudris, D.J., Pirsch, P., Barke, E. (eds.) PATMOS 2000. LNCS, vol. 1918, pp. 243–254. Springer, Heidelberg (2000)
Zervas, N.D., Masselos, K., Goutis, C.E.: Data-reuse exploration for low-power realization of multimedia applications on embedded cores. In: Proc. of 9th Int. Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS 1999), pp. 71–80 (1999)
Bhaskaran, V., Kostantinides, K.: Image and Video Compression Standards. Kluwer Academic Publishers, Dordrecht (1998)
Nam, K.M., Kim, J.-S., Park, R.-H., Shim, Y.S.: A fast hierarchical motion vector estimation algorithm using mean pyramid. IEEE Transactions on Circuits and Systems for Video Technology 5(4), 344–351 (1995)
http://support.xilinx.com/support/sw_manuals/xilinx4/manuals.pdf
Landman, P.: Low-power architectural design methodologies. Doctoral Dissertation, U.C., Berkeley (1994)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2003 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Tatas, K. et al. (2003). Power Optimization Methodology for Multimedia Applications Implementation on Reconfigurable Platforms. In: Chico, J.J., Macii, E. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2003. Lecture Notes in Computer Science, vol 2799. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-39762-5_49
Download citation
DOI: https://doi.org/10.1007/978-3-540-39762-5_49
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-20074-1
Online ISBN: 978-3-540-39762-5
eBook Packages: Springer Book Archive