Abstract
Reconfigurable processors pose unique problems for program safety because of their use of computational approaches that are difficult to integrate into traditional program analyses. The combination of proof-carrying code for verification of standard processor machine code and model-checking for array configurations is explored. This approach is shown to be useful in verifying safety properties including the synchronization of memory accesses by the reconfigurable array and memory access bounds checking.
Partially supported by the NSF Grants nos. CCR-9996150 and ITR-CCR-0113611.
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Cochran, J., Kapur, D., Stefanovic, D. (2003). Model Checking Reconfigurable Processor Configurations for Safety Properties. In: Y. K. Cheung, P., Constantinides, G.A. (eds) Field Programmable Logic and Application. FPL 2003. Lecture Notes in Computer Science, vol 2778. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-45234-8_104
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DOI: https://doi.org/10.1007/978-3-540-45234-8_104
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