Abstract
Generation of hardware architectures directly from dataflow representations is increasingly being considered as research moves toward system level design methodologies. Creation of networks of IP cores to implement actor functionality is a common approach to the problem, but often the memory sub-systems produced using these techniques are inefficiently utilised. This paper explores some of the issues in terms of memory organisation and accesses when developing systems from these high level representations. Using a template matching design study, challenges such as modelling memory reuse and minimising buffer requirements are examined, yielding results with significantly less memory requirements and costly off-chip memory accesses.
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References
Bhattacharyya, S.S.: Hardware/Software Co-Synthesis of DSP Systems. In: Hu., Y.H. (ed.) Programmable Digital Signal Processors: Architecture, Programming, and Applications, pp. 333–378 (2002)
Ha, S., et al.: Hardware-Software Codesign of Multimedia Embedded Systems: the PeaCE Approach. In: 12th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications. IEEE Comput. Soc., Sydney (2006)
Thompson, M., et al.: A Framework for Rapid System-level Exploration, Synthesis, and Programming of Multimedia MP-SoCs. In: Proc. of the 5th IEEE/ACM/IFIP International Conference on HW/SW Codesign of System Synthesis, Aus. (2007)
McAllister, J., Woods, R., Fischaber, S., Malins, E.: Rapid Implementation and Optimisation of DSP Systems on FPGA-Centric Heterogeneous Platforms. Journal of System Architecture 53(8), 511–523 (2007)
Wolf, W.: High Performance Embeddded Computing: Architectures, Applications, and Methodologies. Morgan Kaufmann, San Francisco (2006)
Al-Hashimi, B.: System-on-Chip: Next Generation Electronics. IET, London (2006)
Fischaber, S., McAllister, J., Woods, R., Malins, E.: Muir Hardware Synthesis for Multimedia Applications. IEEE/ACM/IFIP ESTIMedia, pp. 101–106 (2006)
Fischaber, S., Woods, R., McAllister, J.: SoC Memory Hierarchy Derivation from Dataflow Graphs. In: SIPS 2007, Shanghai, China (2007)
Smith, S.W.: The Scientist and Engineer’s Guide to Digital Signal Processing. California Tecnical Pub., San Diego (1997)
Bilsend, G., et al.: Cyclo-Static Data Flow. In: International Conference on Acoustics, Speech, and Signal Processing, vol. 5, pp. 3255-3258 (1995)
McAllister, J., Woods, R., Walke, R., Reilly, D.: Multidimensional DSP Core Synthesis for FPGA. Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology 43(2), 207–221 (2006)
Denolf, K., et al.: Exploiting the Expressiveness of Cyclo-Static Dataflow to Model Multimedia Implementations. EURASIP Journal on Advances in Signal Processing (2007)
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Fischaber, S., McAllister, J., Woods, R. (2008). Memory-Centric Hardware Synthesis from Dataflow Models. In: Bereković, M., Dimopoulos, N., Wong, S. (eds) Embedded Computer Systems: Architectures, Modeling, and Simulation. SAMOS 2008. Lecture Notes in Computer Science, vol 5114. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-70550-5_22
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DOI: https://doi.org/10.1007/978-3-540-70550-5_22
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-70549-9
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