Location via proxy:   [ UP ]  
[Report a bug]   [Manage cookies]                
Skip to main content

Design Issues in Parallel Array Languages for Shared Memory

  • Conference paper
Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS 2008)

Part of the book series: Lecture Notes in Computer Science ((LNTCS,volume 5114))

Included in the following conference series:

Abstract

The Hierarchically Tiled Array (HTA) is a data type that facilitates the definition and manipulation of arrays partitioned into tiles. The data type allows to exploit those tiles to attain both locality and parallelism. Parallel programs written with HTAs are based in data parallelism, and provide the programmer with a single-threaded view of the execution. In our experience, HTAs help to develop parallel codes in a much more productive way than other parallel programming approaches. While we have worked extensively with HTAs in distributed memory environments, only recently have we began to consider their adaption to shared memory environments such as those found in multicore systems. In this paper we review the design issues, opportunities and challenges that this migration raises.

This material is based upon work supported by the National Science Foundation under Awards CCF 0702260 and CNS 0509432. Basilio B. Fraguela was partially supported by the Ministry of Education and Science of Spain, FEDER funds of the European Union (Projects TIN2004-07797-C02-02 and TIN2007-67537-C03-02).

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Subscribe and save

Springer+ Basic
$34.99 /Month
  • Get 10 units per month
  • Download Article/Chapter or eBook
  • 1 Unit = 1 Article or 1 Chapter
  • Cancel anytime
Subscribe now

Buy Now

Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 39.99
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 54.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

Similar content being viewed by others

References

  1. Barnes, G.H., Brown, R.M., Kato, M., Kuck, D., Slotnick, D., Stokes, R.: The ILLIAC IV Computer. IEEE Transactions on Computers 8(17), 746–757 (1968)

    Article  Google Scholar 

  2. McKellar, A.C., Coffman, J.E.G.: Organizing Matrices and Matrix Operations for Paged Memory Systems. Communications of the ACM 12(3), 153–165 (1969)

    Article  MATH  Google Scholar 

  3. Wolf, M.E., Lam, M.S.: A Data Locality Optimizing Algorithm. In: Proc. of the Conf. on Programming Language Design and Implementation, pp. 30–44 (1991)

    Google Scholar 

  4. High Performance Fortran Forum. High Performance Fortran Specification Version 2.0 (January 1997)

    Google Scholar 

  5. Chamberlain, B., Choi, S.: The Case for High Level Parallel Programming in ZPL. IEEE Computational Science and Engineering 5(3), 76–86 (1998)

    Article  Google Scholar 

  6. Carlson, W., Draper, J., Culler, D., Yelick, K., Brooks, E., Warren, K.: Introduction to UPC and Language Specification. Technical Report CCS-TR-99-157, IDA Center for Computing Sciences (1999)

    Google Scholar 

  7. Numrich, R.W., Reid, J.: Co-array Fortran for Parallel Programming. SIGPLAN Fortran Forum 17(2), 1–31 (1998)

    Article  Google Scholar 

  8. Bikshandi, G., Guo, J., Hoeflinger, D., Almasi, G., Fraguela, B.B., Garzarán, M.J., Padua, D., von Praun, C.: Programming for Parallelism and Locality with Hierarchically Tiled Arrays. In: PPoPP 2006: Proc. of the ACM SIGPLAN Symp. on Principles and Practice of Parallel Programming, pp. 48–57 (March 2006)

    Google Scholar 

  9. Guo, J., Bikshandi, G., Fraguela, B.B., Garzarán, M.J., Padua, D.: Programming with Tiles. In: PPoPP 2008: Proc. of the ACM SIGPLAN Symp. on Principles and Practice of Parallel Programming, pp. 111–122 (February 2008)

    Google Scholar 

  10. NAS Parallel Benchmarks, http://www.nas.nasa.gov/Software/NPB/

  11. Reinders, J.: Intel Threading Building Blocks: Outfitting C++ for Multi-core Processor Parallelism, 1st edn. O’Reilly, Sebastopol (July 2007)

    Google Scholar 

  12. Butenhof, D.R.: Programming with POSIX Threads. Addison Wesley, Reading (1997)

    Google Scholar 

  13. Chandra, R., Dagum, L., Kohr, D., Maydan, D., McDonald, J., Menon, R.: Parallel programming in OpenMP. Morgan Kaufmann Publishers, San Francisco (2001)

    Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Editor information

Mladen Bereković Nikitas Dimopoulos Stephan Wong

Rights and permissions

Reprints and permissions

Copyright information

© 2008 Springer-Verlag Berlin Heidelberg

About this paper

Cite this paper

Brodman, J., Fraguela, B.B., Garzarán, M.J., Padua, D. (2008). Design Issues in Parallel Array Languages for Shared Memory. In: Bereković, M., Dimopoulos, N., Wong, S. (eds) Embedded Computer Systems: Architectures, Modeling, and Simulation. SAMOS 2008. Lecture Notes in Computer Science, vol 5114. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-70550-5_24

Download citation

  • DOI: https://doi.org/10.1007/978-3-540-70550-5_24

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-70549-9

  • Online ISBN: 978-3-540-70550-5

  • eBook Packages: Computer ScienceComputer Science (R0)

Publish with us

Policies and ethics