Abstract
The Hierarchically Tiled Array (HTA) is a data type that facilitates the definition and manipulation of arrays partitioned into tiles. The data type allows to exploit those tiles to attain both locality and parallelism. Parallel programs written with HTAs are based in data parallelism, and provide the programmer with a single-threaded view of the execution. In our experience, HTAs help to develop parallel codes in a much more productive way than other parallel programming approaches. While we have worked extensively with HTAs in distributed memory environments, only recently have we began to consider their adaption to shared memory environments such as those found in multicore systems. In this paper we review the design issues, opportunities and challenges that this migration raises.
This material is based upon work supported by the National Science Foundation under Awards CCF 0702260 and CNS 0509432. Basilio B. Fraguela was partially supported by the Ministry of Education and Science of Spain, FEDER funds of the European Union (Projects TIN2004-07797-C02-02 and TIN2007-67537-C03-02).
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References
Barnes, G.H., Brown, R.M., Kato, M., Kuck, D., Slotnick, D., Stokes, R.: The ILLIAC IV Computer. IEEE Transactions on Computers 8(17), 746–757 (1968)
McKellar, A.C., Coffman, J.E.G.: Organizing Matrices and Matrix Operations for Paged Memory Systems. Communications of the ACM 12(3), 153–165 (1969)
Wolf, M.E., Lam, M.S.: A Data Locality Optimizing Algorithm. In: Proc. of the Conf. on Programming Language Design and Implementation, pp. 30–44 (1991)
High Performance Fortran Forum. High Performance Fortran Specification Version 2.0 (January 1997)
Chamberlain, B., Choi, S.: The Case for High Level Parallel Programming in ZPL. IEEE Computational Science and Engineering 5(3), 76–86 (1998)
Carlson, W., Draper, J., Culler, D., Yelick, K., Brooks, E., Warren, K.: Introduction to UPC and Language Specification. Technical Report CCS-TR-99-157, IDA Center for Computing Sciences (1999)
Numrich, R.W., Reid, J.: Co-array Fortran for Parallel Programming. SIGPLAN Fortran Forum 17(2), 1–31 (1998)
Bikshandi, G., Guo, J., Hoeflinger, D., Almasi, G., Fraguela, B.B., Garzarán, M.J., Padua, D., von Praun, C.: Programming for Parallelism and Locality with Hierarchically Tiled Arrays. In: PPoPP 2006: Proc. of the ACM SIGPLAN Symp. on Principles and Practice of Parallel Programming, pp. 48–57 (March 2006)
Guo, J., Bikshandi, G., Fraguela, B.B., Garzarán, M.J., Padua, D.: Programming with Tiles. In: PPoPP 2008: Proc. of the ACM SIGPLAN Symp. on Principles and Practice of Parallel Programming, pp. 111–122 (February 2008)
NAS Parallel Benchmarks, http://www.nas.nasa.gov/Software/NPB/
Reinders, J.: Intel Threading Building Blocks: Outfitting C++ for Multi-core Processor Parallelism, 1st edn. O’Reilly, Sebastopol (July 2007)
Butenhof, D.R.: Programming with POSIX Threads. Addison Wesley, Reading (1997)
Chandra, R., Dagum, L., Kohr, D., Maydan, D., McDonald, J., Menon, R.: Parallel programming in OpenMP. Morgan Kaufmann Publishers, San Francisco (2001)
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Brodman, J., Fraguela, B.B., Garzarán, M.J., Padua, D. (2008). Design Issues in Parallel Array Languages for Shared Memory. In: Bereković, M., Dimopoulos, N., Wong, S. (eds) Embedded Computer Systems: Architectures, Modeling, and Simulation. SAMOS 2008. Lecture Notes in Computer Science, vol 5114. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-70550-5_24
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DOI: https://doi.org/10.1007/978-3-540-70550-5_24
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